blob: 673bc2c95f7a341199edf31f89948c444266ded5 [file] [log] [blame]
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +02001/*
2 * (C) Copyright 2002
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 * Keith Outwater, keith_outwater@mvis.com.
5 *
6 * (C) Copyright 2011
7 * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 *
27 */
28
29#include <common.h>
30#include <ACEX1K.h>
31#include <command.h>
32#include "mergerbox.h"
33#include "fpga.h"
34
35Altera_CYC2_Passive_Serial_fns altera_fns = {
36 fpga_null_fn,
37 fpga_config_fn,
38 fpga_status_fn,
39 fpga_done_fn,
40 fpga_wr_fn,
41 fpga_null_fn,
42 fpga_null_fn,
43};
44
45Altera_desc cyclone2 = {
46 Altera_CYC2,
47 passive_serial,
48 Altera_EP2C20_SIZE,
49 (void *) &altera_fns,
50 NULL,
51 0
52};
53
54DECLARE_GLOBAL_DATA_PTR;
55
56int mergerbox_init_fpga(void)
57{
58 debug("Initialize FPGA interface\n");
59 fpga_init();
60 fpga_add(fpga_altera, &cyclone2);
61
62 return 1;
63}
64
65int fpga_null_fn(int cookie)
66{
67 return 0;
68}
69
70int fpga_config_fn(int assert, int flush, int cookie)
71{
72 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
73 volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
74 u32 dvo = gpio->dat;
75
76 dvo &= ~FPGA_CONFIG;
77 gpio->dat = dvo;
78 udelay(5);
79 dvo |= FPGA_CONFIG;
80 gpio->dat = dvo;
81
82 return assert;
83}
84
85int fpga_done_fn(int cookie)
86{
87 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
88 volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
89 int result = 0;
90
91 udelay(10);
92 debug("CONF_DONE check ... ");
93 if (gpio->dat & FPGA_CONF_DONE) {
94 debug("high\n");
95 result = 1;
96 } else
97 debug("low\n");
98
99 return result;
100}
101
102int fpga_status_fn(int cookie)
103{
104 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
105 volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
106 int result = 0;
107
108 debug("STATUS check ... ");
109 if (gpio->dat & FPGA_STATUS) {
110 debug("high\n");
111 result = 1;
112 } else
113 debug("low\n");
114
115 return result;
116}
117
118int fpga_clk_fn(int assert_clk, int flush, int cookie)
119{
120 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
121 volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
122 u32 dvo = gpio->dat;
123
124 debug("CLOCK %s\n", assert_clk ? "high" : "low");
125 if (assert_clk)
126 dvo |= FPGA_CCLK;
127 else
128 dvo &= ~FPGA_CCLK;
129
130 if (flush)
131 gpio->dat = dvo;
132
133 return assert_clk;
134}
135
136static inline int _write_fpga(u8 val, int dump)
137{
138 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
139 volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
140 int i;
141 u32 dvo = gpio->dat;
142
143 if (dump)
144 debug(" %02x -> ", val);
145 for (i = 0; i < 8; i++) {
146 dvo &= ~FPGA_CCLK;
147 gpio->dat = dvo;
148 dvo &= ~FPGA_DIN;
149 if (dump)
150 debug("%d ", val&1);
151 if (val & 1)
152 dvo |= FPGA_DIN;
153 gpio->dat = dvo;
154 dvo |= FPGA_CCLK;
155 gpio->dat = dvo;
156 val >>= 1;
157 }
158 if (dump)
159 debug("\n");
160
161 return 0;
162}
163
164int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
165{
166 unsigned char *data = (unsigned char *) buf;
167 int i;
168
169 debug("fpga_wr: buf %p / size %d\n", buf, len);
170 for (i = 0; i < len; i++)
171 _write_fpga(data[i], 0);
172 debug("\n");
173
174 return FPGA_SUCCESS;
175}