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Scott Wood96b8a052007-04-16 14:54:15 -05001/*
Scott Woode8d3ca82010-08-30 18:04:52 -05002 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
Scott Wood96b8a052007-04-16 14:54:15 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
Scott Wood96b8a052007-04-16 14:54:15 -050021 */
22/*
23 * mpc8313epb board configuration file
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 */
32#define CONFIG_E300 1
Peter Tyser0f898602009-05-22 17:23:24 -050033#define CONFIG_MPC83xx 1
Peter Tyser2c7920a2009-05-22 17:23:25 -050034#define CONFIG_MPC831x 1
Scott Wood96b8a052007-04-16 14:54:15 -050035#define CONFIG_MPC8313 1
36#define CONFIG_MPC8313ERDB 1
37
Scott Wood22f44422012-12-06 13:33:18 +000038#ifdef CONFIG_NAND
39#define CONFIG_SPL
40#define CONFIG_SPL_INIT_MINIMAL
41#define CONFIG_SPL_SERIAL_SUPPORT
42#define CONFIG_SPL_NAND_SUPPORT
43#define CONFIG_SPL_NAND_MINIMAL
44#define CONFIG_SPL_FLUSH_IMAGE
45#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
46#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
47
48#ifdef CONFIG_SPL_BUILD
49#define CONFIG_NS16550_MIN_FUNCTIONS
50#endif
51
52#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
53#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
54#define CONFIG_SPL_MAX_SIZE (4 * 1024)
Benoît Thébaudeau6113d3f2013-04-11 09:35:49 +000055#define CONFIG_SPL_PAD_TO 0x4000
Scott Wood22f44422012-12-06 13:33:18 +000056
Scott Woodf1c574d2010-11-24 13:28:40 +000057#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
58#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
59#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
60#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
61#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
62#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
63
Scott Wood22f44422012-12-06 13:33:18 +000064#ifdef CONFIG_SPL_BUILD
Scott Woodf1c574d2010-11-24 13:28:40 +000065#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
Scott Wood22f44422012-12-06 13:33:18 +000066#endif
67
68#endif /* CONFIG_NAND */
Scott Woodf1c574d2010-11-24 13:28:40 +000069
Wolfgang Denk2ae18242010-10-06 09:05:45 +020070#ifndef CONFIG_SYS_TEXT_BASE
71#define CONFIG_SYS_TEXT_BASE 0xFE000000
72#endif
73
Scott Woodf1c574d2010-11-24 13:28:40 +000074#ifndef CONFIG_SYS_MONITOR_BASE
75#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
76#endif
77
Scott Wood96b8a052007-04-16 14:54:15 -050078#define CONFIG_PCI
Becky Bruce0914f482010-06-17 11:37:18 -050079#define CONFIG_FSL_ELBC 1
Scott Wood96b8a052007-04-16 14:54:15 -050080
Timur Tabi89c77842008-02-08 13:15:55 -060081#define CONFIG_MISC_INIT_R
82
83/*
84 * On-board devices
York Sun4ce1e232008-05-15 15:26:27 -050085 *
86 * TSEC1 is VSC switch
87 * TSEC2 is SoC TSEC
Timur Tabi89c77842008-02-08 13:15:55 -060088 */
89#define CONFIG_VSC7385_ENET
York Sun4ce1e232008-05-15 15:26:27 -050090#define CONFIG_TSEC2
Timur Tabi89c77842008-02-08 13:15:55 -060091
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#ifdef CONFIG_SYS_66MHZ
Kim Phillips5c5d3242007-04-25 12:34:38 -050093#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#elif defined(CONFIG_SYS_33MHZ)
Kim Phillips5c5d3242007-04-25 12:34:38 -050095#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
Scott Wood96b8a052007-04-16 14:54:15 -050096#else
97#error Unknown oscillator frequency.
98#endif
99
100#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
101
Joe Hershberger0eaf8f92011-11-11 15:55:38 -0600102#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
103#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */
Scott Wood96b8a052007-04-16 14:54:15 -0500104
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_IMMR 0xE0000000
Scott Wood96b8a052007-04-16 14:54:15 -0500106
Scott Wood22f44422012-12-06 13:33:18 +0000107#if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
Scott Woode4c09502008-06-30 14:13:28 -0500109#endif
110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_MEMTEST_START 0x00001000
112#define CONFIG_SYS_MEMTEST_END 0x07f00000
Scott Wood96b8a052007-04-16 14:54:15 -0500113
114/* Early revs of this board will lock up hard when attempting
115 * to access the PMC registers, unless a JTAG debugger is
116 * connected, or some resistor modifications are made.
117 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
Scott Wood96b8a052007-04-16 14:54:15 -0500119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
121#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Scott Wood96b8a052007-04-16 14:54:15 -0500122
123/*
Timur Tabi89c77842008-02-08 13:15:55 -0600124 * Device configurations
125 */
126
127/* Vitesse 7385 */
128
129#ifdef CONFIG_VSC7385_ENET
130
York Sun4ce1e232008-05-15 15:26:27 -0500131#define CONFIG_TSEC1
Timur Tabi89c77842008-02-08 13:15:55 -0600132
133/* The flash address and size of the VSC7385 firmware image */
134#define CONFIG_VSC7385_IMAGE 0xFE7FE000
135#define CONFIG_VSC7385_IMAGE_SIZE 8192
136
137#endif
138
139/*
Scott Wood96b8a052007-04-16 14:54:15 -0500140 * DDR Setup
141 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500142#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
144#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Scott Wood96b8a052007-04-16 14:54:15 -0500145
146/*
147 * Manually set up DDR parameters, as this board does not
148 * seem to have the SPD connected to I2C.
149 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500150#define CONFIG_SYS_DDR_SIZE 128 /* MB */
Joe Hershberger2e651b22011-10-11 23:57:31 -0500151#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500152 | CSCONFIG_ODT_RD_NEVER \
153 | CSCONFIG_ODT_WR_ONLY_CURRENT \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500154 | CSCONFIG_ROW_BIT_13 \
155 | CSCONFIG_COL_BIT_10)
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530156 /* 0x80010102 */
Scott Wood96b8a052007-04-16 14:54:15 -0500157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershberger261c07b2011-10-11 23:57:10 -0500159#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
160 | (0 << TIMING_CFG0_WRT_SHIFT) \
161 | (0 << TIMING_CFG0_RRT_SHIFT) \
162 | (0 << TIMING_CFG0_WWT_SHIFT) \
163 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
164 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
165 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
166 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Scott Wood96b8a052007-04-16 14:54:15 -0500167 /* 0x00220802 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500168#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
169 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
170 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
171 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
172 | (10 << TIMING_CFG1_REFREC_SHIFT) \
173 | (3 << TIMING_CFG1_WRREC_SHIFT) \
174 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
175 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530176 /* 0x3835a322 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500177#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
178 | (5 << TIMING_CFG2_CPO_SHIFT) \
179 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
180 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
181 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
182 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
183 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530184 /* 0x129048c6 */ /* P9-45,may need tuning */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500185#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
186 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530187 /* 0x05100500 */
Scott Wood96b8a052007-04-16 14:54:15 -0500188#if defined(CONFIG_DDR_2T_TIMING)
Joe Hershberger261c07b2011-10-11 23:57:10 -0500189#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500190 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500191 | SDRAM_CFG_DBW_32 \
192 | SDRAM_CFG_2T_EN)
193 /* 0x43088000 */
Scott Wood96b8a052007-04-16 14:54:15 -0500194#else
Joe Hershberger261c07b2011-10-11 23:57:10 -0500195#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500196 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500197 | SDRAM_CFG_DBW_32)
Scott Wood96b8a052007-04-16 14:54:15 -0500198 /* 0x43080000 */
199#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_SDRAM_CFG2 0x00401000
Scott Wood96b8a052007-04-16 14:54:15 -0500201/* set burst length to 8 for 32-bit data path */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500202#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
203 | (0x0632 << SDRAM_MODE_SD_SHIFT))
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530204 /* 0x44480632 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500205#define CONFIG_SYS_DDR_MODE_2 0x8000C000
Scott Wood96b8a052007-04-16 14:54:15 -0500206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Scott Wood96b8a052007-04-16 14:54:15 -0500208 /*0x02000000*/
Joe Hershberger261c07b2011-10-11 23:57:10 -0500209#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
Scott Wood96b8a052007-04-16 14:54:15 -0500210 | DDRCDR_PZ_NOMZ \
211 | DDRCDR_NZ_NOMZ \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500212 | DDRCDR_M_ODR)
Scott Wood96b8a052007-04-16 14:54:15 -0500213
214/*
215 * FLASH on the Local Bus
216 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500217#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
218#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500220#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
221#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
222#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
223#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
Scott Wood96b8a052007-04-16 14:54:15 -0500224
Joe Hershberger261c07b2011-10-11 23:57:10 -0500225#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500226 | BR_PS_16 /* 16 bit port */ \
227 | BR_MS_GPCM /* MSEL = GPCM */ \
228 | BR_V) /* valid */
229#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Scott Wood96b8a052007-04-16 14:54:15 -0500230 | OR_GPCM_XACS \
231 | OR_GPCM_SCY_9 \
232 | OR_GPCM_EHTR \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500233 | OR_GPCM_EAD)
Scott Wood96b8a052007-04-16 14:54:15 -0500234 /* 0xFF006FF7 TODO SLOW 16 MB flash size */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500235 /* window base at flash base */
236#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500237 /* 16 MB window size */
238#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
Scott Wood96b8a052007-04-16 14:54:15 -0500239
Joe Hershberger261c07b2011-10-11 23:57:10 -0500240#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
241#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
Scott Wood96b8a052007-04-16 14:54:15 -0500242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
244#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Scott Wood96b8a052007-04-16 14:54:15 -0500245
Joe Hershberger261c07b2011-10-11 23:57:10 -0500246#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
Scott Wood22f44422012-12-06 13:33:18 +0000247 !defined(CONFIG_SPL_BUILD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_RAMBOOT
Scott Wood96b8a052007-04-16 14:54:15 -0500249#endif
250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershberger261c07b2011-10-11 23:57:10 -0500252#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
253#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Scott Wood96b8a052007-04-16 14:54:15 -0500254
Joe Hershberger261c07b2011-10-11 23:57:10 -0500255#define CONFIG_SYS_GBL_DATA_OFFSET \
256 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Scott Wood96b8a052007-04-16 14:54:15 -0500258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500260#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
261#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Scott Wood96b8a052007-04-16 14:54:15 -0500262
263/*
264 * Local Bus LCRR and LBCR regs
265 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500266#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
267#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Joe Hershberger261c07b2011-10-11 23:57:10 -0500268#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
269 | (0xFF << LBCR_BMT_SHIFT) \
270 | 0xF) /* 0x0004ff0f */
Scott Wood96b8a052007-04-16 14:54:15 -0500271
Joe Hershberger261c07b2011-10-11 23:57:10 -0500272 /* LB refresh timer prescal, 266MHz/32 */
273#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
Scott Wood96b8a052007-04-16 14:54:15 -0500274
Marcel Ziswiler7817cb22007-12-30 03:30:46 +0100275/* drivers/mtd/nand/nand.c */
Scott Wood22f44422012-12-06 13:33:18 +0000276#if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_NAND_BASE 0xFFF00000
Scott Woode4c09502008-06-30 14:13:28 -0500278#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_NAND_BASE 0xE2800000
Scott Woode4c09502008-06-30 14:13:28 -0500280#endif
281
Scott Woode8d3ca82010-08-30 18:04:52 -0500282#define CONFIG_MTD_DEVICE
283#define CONFIG_MTD_PARTITION
284#define CONFIG_CMD_MTDPARTS
285#define MTDIDS_DEFAULT "nand0=e2800000.flash"
Joe Hershberger261c07b2011-10-11 23:57:10 -0500286#define MTDPARTS_DEFAULT \
Scott Woodc947c122012-01-04 16:48:26 -0600287 "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
Scott Woode8d3ca82010-08-30 18:04:52 -0500288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_MAX_NAND_DEVICE 1
Scott Wood96b8a052007-04-16 14:54:15 -0500290#define CONFIG_MTD_NAND_VERIFY_WRITE
Scott Woodacdab5c2008-06-26 14:06:52 -0500291#define CONFIG_CMD_NAND 1
292#define CONFIG_NAND_FSL_ELBC 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500294#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
Scott Wood96b8a052007-04-16 14:54:15 -0500295
Scott Woode4c09502008-06-30 14:13:28 -0500296
Joe Hershberger261c07b2011-10-11 23:57:10 -0500297#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500298 | BR_DECC_CHK_GEN /* Use HW ECC */ \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500299 | BR_PS_8 /* 8 bit port */ \
Wolfgang Denka7676ea2007-05-16 01:16:53 +0200300 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500301 | BR_V) /* valid */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500302#define CONFIG_SYS_NAND_OR_PRELIM \
303 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
Scott Wood96b8a052007-04-16 14:54:15 -0500304 | OR_FCM_CSCT \
305 | OR_FCM_CST \
306 | OR_FCM_CHT \
307 | OR_FCM_SCY_1 \
308 | OR_FCM_TRLX \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500309 | OR_FCM_EHTR)
Scott Wood96b8a052007-04-16 14:54:15 -0500310 /* 0xFFFF8396 */
Scott Woode4c09502008-06-30 14:13:28 -0500311
Scott Wood22f44422012-12-06 13:33:18 +0000312#ifdef CONFIG_NAND
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
314#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
315#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
316#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
Scott Woode4c09502008-06-30 14:13:28 -0500317#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
319#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
320#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
321#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
Scott Woode4c09502008-06-30 14:13:28 -0500322#endif
323
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500325#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Scott Wood96b8a052007-04-16 14:54:15 -0500326
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
328#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
Scott Woode4c09502008-06-30 14:13:28 -0500329
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500330/* local bus write LED / read status buffer (BCSR) mapping */
331#define CONFIG_SYS_BCSR_ADDR 0xFA000000
332#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
333 /* map at 0xFA000000 on LCS3 */
334#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
335 | BR_PS_8 /* 8 bit port */ \
336 | BR_MS_GPCM /* MSEL = GPCM */ \
337 | BR_V) /* valid */
338 /* 0xFA000801 */
339#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
340 | OR_GPCM_CSNT \
341 | OR_GPCM_ACS_DIV2 \
342 | OR_GPCM_XACS \
343 | OR_GPCM_SCY_15 \
344 | OR_GPCM_TRLX_SET \
345 | OR_GPCM_EHTR_SET \
346 | OR_GPCM_EAD)
347 /* 0xFFFF8FF7 */
348#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
349#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Scott Wood96b8a052007-04-16 14:54:15 -0500350
Timur Tabi89c77842008-02-08 13:15:55 -0600351/* Vitesse 7385 */
352
Timur Tabi89c77842008-02-08 13:15:55 -0600353#ifdef CONFIG_VSC7385_ENET
354
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500355 /* VSC7385 Base address on LCS2 */
356#define CONFIG_SYS_VSC7385_BASE 0xF0000000
357#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
358
359#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
360 | BR_PS_8 /* 8 bit port */ \
361 | BR_MS_GPCM /* MSEL = GPCM */ \
362 | BR_V) /* valid */
363#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
364 | OR_GPCM_CSNT \
365 | OR_GPCM_XACS \
366 | OR_GPCM_SCY_15 \
367 | OR_GPCM_SETA \
368 | OR_GPCM_TRLX_SET \
369 | OR_GPCM_EHTR_SET \
370 | OR_GPCM_EAD)
371 /* 0xFFFE09FF */
372
Joe Hershberger261c07b2011-10-11 23:57:10 -0500373 /* Access window base at VSC7385 base */
374#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500375#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
Timur Tabi89c77842008-02-08 13:15:55 -0600376
377#endif
378
Scott Wood96b8a052007-04-16 14:54:15 -0500379/* pass open firmware flat tree */
Kim Phillips35cc4e42007-08-15 22:30:39 -0500380#define CONFIG_OF_LIBFDT 1
Scott Wood96b8a052007-04-16 14:54:15 -0500381#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600382#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Scott Wood96b8a052007-04-16 14:54:15 -0500383
Joe Hershberger0eaf8f92011-11-11 15:55:38 -0600384#define CONFIG_MPC83XX_GPIO 1
385#define CONFIG_CMD_GPIO 1
386
Scott Wood96b8a052007-04-16 14:54:15 -0500387/*
388 * Serial Port
389 */
390#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_NS16550
392#define CONFIG_SYS_NS16550_SERIAL
393#define CONFIG_SYS_NS16550_REG_SIZE 1
Scott Wood96b8a052007-04-16 14:54:15 -0500394
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_BAUDRATE_TABLE \
Scott Wood96b8a052007-04-16 14:54:15 -0500396 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
397
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
399#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Scott Wood96b8a052007-04-16 14:54:15 -0500400
401/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_HUSH_PARSER
Scott Wood96b8a052007-04-16 14:54:15 -0500403
404/* I2C */
405#define CONFIG_HARD_I2C /* I2C with hardware support*/
406#define CONFIG_FSL_I2C
407#define CONFIG_I2C_MULTI_BUS
Joe Hershberger261c07b2011-10-11 23:57:10 -0500408#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
409#define CONFIG_SYS_I2C_SLAVE 0x7F
410#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
411#define CONFIG_SYS_I2C_OFFSET 0x3000
412#define CONFIG_SYS_I2C2_OFFSET 0x3100
Scott Wood96b8a052007-04-16 14:54:15 -0500413
Scott Wood96b8a052007-04-16 14:54:15 -0500414/*
415 * General PCI
416 * Addresses are mapped 1-1.
417 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
419#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
420#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
421#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
422#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
423#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
424#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
425#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
426#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Scott Wood96b8a052007-04-16 14:54:15 -0500427
428#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Scott Wood96b8a052007-04-16 14:54:15 -0500430
431/*
Timur Tabi89c77842008-02-08 13:15:55 -0600432 * TSEC
Scott Wood96b8a052007-04-16 14:54:15 -0500433 */
434#define CONFIG_TSEC_ENET /* TSEC ethernet support */
435
Timur Tabi89c77842008-02-08 13:15:55 -0600436#define CONFIG_GMII /* MII PHY management */
437
438#ifdef CONFIG_TSEC1
439#define CONFIG_HAS_ETH0
440#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Timur Tabi89c77842008-02-08 13:15:55 -0600442#define TSEC1_PHY_ADDR 0x1c
443#define TSEC1_FLAGS TSEC_GIGABIT
444#define TSEC1_PHYIDX 0
Scott Wood96b8a052007-04-16 14:54:15 -0500445#endif
446
Timur Tabi89c77842008-02-08 13:15:55 -0600447#ifdef CONFIG_TSEC2
448#define CONFIG_HAS_ETH1
Kim Phillips255a35772007-05-16 16:52:19 -0500449#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi89c77842008-02-08 13:15:55 -0600451#define TSEC2_PHY_ADDR 4
452#define TSEC2_FLAGS TSEC_GIGABIT
453#define TSEC2_PHYIDX 0
454#endif
455
Scott Wood96b8a052007-04-16 14:54:15 -0500456
457/* Options are: TSEC[0-1] */
458#define CONFIG_ETHPRIME "TSEC1"
459
460/*
461 * Configure on-board RTC
462 */
463#define CONFIG_RTC_DS1337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Scott Wood96b8a052007-04-16 14:54:15 -0500465
466/*
467 * Environment
468 */
Scott Wood22f44422012-12-06 13:33:18 +0000469#if defined(CONFIG_NAND)
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200470 #define CONFIG_ENV_IS_IN_NAND 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200471 #define CONFIG_ENV_OFFSET (512 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200473 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
474 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
475 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
Joe Hershberger261c07b2011-10-11 23:57:10 -0500476 #define CONFIG_ENV_OFFSET_REDUND \
477 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#elif !defined(CONFIG_SYS_RAMBOOT)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200479 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger261c07b2011-10-11 23:57:10 -0500480 #define CONFIG_ENV_ADDR \
481 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200482 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
483 #define CONFIG_ENV_SIZE 0x2000
Scott Wood96b8a052007-04-16 14:54:15 -0500484
485/* Address and size of Redundant Environment Sector */
486#else
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200487 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200489 #define CONFIG_ENV_SIZE 0x2000
Scott Wood96b8a052007-04-16 14:54:15 -0500490#endif
491
492#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Scott Wood96b8a052007-04-16 14:54:15 -0500494
Jon Loeliger8ea54992007-07-04 22:30:06 -0500495/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500496 * BOOTP options
497 */
498#define CONFIG_BOOTP_BOOTFILESIZE
499#define CONFIG_BOOTP_BOOTPATH
500#define CONFIG_BOOTP_GATEWAY
501#define CONFIG_BOOTP_HOSTNAME
502
503
504/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500505 * Command line configuration.
506 */
507#include <config_cmd_default.h>
508
509#define CONFIG_CMD_PING
510#define CONFIG_CMD_DHCP
511#define CONFIG_CMD_I2C
512#define CONFIG_CMD_MII
513#define CONFIG_CMD_DATE
514#define CONFIG_CMD_PCI
515
Scott Wood22f44422012-12-06 13:33:18 +0000516#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500517 #undef CONFIG_CMD_SAVEENV
Jon Loeliger8ea54992007-07-04 22:30:06 -0500518 #undef CONFIG_CMD_LOADS
519#endif
Scott Wood96b8a052007-04-16 14:54:15 -0500520
521#define CONFIG_CMDLINE_EDITING 1
Kim Phillipsa059e902010-04-15 17:36:05 -0500522#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Scott Wood96b8a052007-04-16 14:54:15 -0500523
524/*
525 * Miscellaneous configurable options
526 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_LONGHELP /* undef to save memory */
528#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
529#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
530#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Scott Wood96b8a052007-04-16 14:54:15 -0500531
Joe Hershberger261c07b2011-10-11 23:57:10 -0500532 /* Print Buffer Size */
533#define CONFIG_SYS_PBSIZE \
534 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
535#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
536 /* Boot Argument Buffer Size */
537#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
538#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Scott Wood96b8a052007-04-16 14:54:15 -0500539
540/*
541 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700542 * have to be in the first 256 MB of memory, since this is
Scott Wood96b8a052007-04-16 14:54:15 -0500543 * the maximum mapped by the Linux kernel during initialization.
544 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500545 /* Initial Memory map for Linux*/
546#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Scott Wood96b8a052007-04-16 14:54:15 -0500547
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200548#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
Scott Wood96b8a052007-04-16 14:54:15 -0500549
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200550#ifdef CONFIG_SYS_66MHZ
Scott Wood96b8a052007-04-16 14:54:15 -0500551
552/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
553/* 0x62040000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200554#define CONFIG_SYS_HRCW_LOW (\
Scott Wood96b8a052007-04-16 14:54:15 -0500555 0x20000000 /* reserved, must be set */ |\
556 HRCWL_DDRCM |\
557 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
558 HRCWL_DDR_TO_SCB_CLK_2X1 |\
559 HRCWL_CSB_TO_CLKIN_2X1 |\
560 HRCWL_CORE_TO_CSB_2X1)
561
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200562#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
Scott Woode4c09502008-06-30 14:13:28 -0500563
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200564#elif defined(CONFIG_SYS_33MHZ)
Scott Wood96b8a052007-04-16 14:54:15 -0500565
566/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
567/* 0x65040000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200568#define CONFIG_SYS_HRCW_LOW (\
Scott Wood96b8a052007-04-16 14:54:15 -0500569 0x20000000 /* reserved, must be set */ |\
570 HRCWL_DDRCM |\
571 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
572 HRCWL_DDR_TO_SCB_CLK_2X1 |\
573 HRCWL_CSB_TO_CLKIN_5X1 |\
574 HRCWL_CORE_TO_CSB_2X1)
575
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200576#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
Scott Woode4c09502008-06-30 14:13:28 -0500577
Scott Wood96b8a052007-04-16 14:54:15 -0500578#endif
579
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200580#define CONFIG_SYS_HRCW_HIGH_BASE (\
Scott Wood96b8a052007-04-16 14:54:15 -0500581 HRCWH_PCI_HOST |\
582 HRCWH_PCI1_ARBITER_ENABLE |\
583 HRCWH_CORE_ENABLE |\
Scott Wood96b8a052007-04-16 14:54:15 -0500584 HRCWH_BOOTSEQ_DISABLE |\
585 HRCWH_SW_WATCHDOG_DISABLE |\
Scott Wood96b8a052007-04-16 14:54:15 -0500586 HRCWH_TSEC1M_IN_RGMII |\
587 HRCWH_TSEC2M_IN_RGMII |\
Scott Woode4c09502008-06-30 14:13:28 -0500588 HRCWH_BIG_ENDIAN)
589
Scott Wood22f44422012-12-06 13:33:18 +0000590#ifdef CONFIG_NAND
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200591#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
Wolfgang Denk4b070802008-08-14 14:41:06 +0200592 HRCWH_FROM_0XFFF00100 |\
593 HRCWH_ROM_LOC_NAND_SP_8BIT |\
594 HRCWH_RL_EXT_NAND)
Scott Woode4c09502008-06-30 14:13:28 -0500595#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200596#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
Wolfgang Denk4b070802008-08-14 14:41:06 +0200597 HRCWH_FROM_0X00000100 |\
598 HRCWH_ROM_LOC_LOCAL_16BIT |\
599 HRCWH_RL_EXT_LEGACY)
Scott Woode4c09502008-06-30 14:13:28 -0500600#endif
Scott Wood96b8a052007-04-16 14:54:15 -0500601
602/* System IO Config */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200603#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
Joe Hershberger0eaf8f92011-11-11 15:55:38 -0600604 /* Enable Internal USB Phy and GPIO on LCD Connector */
605#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
Scott Wood96b8a052007-04-16 14:54:15 -0500606
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200607#define CONFIG_SYS_HID0_INIT 0x000000000
608#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
Kim Phillips1a2e2032010-04-20 19:37:54 -0500609 HID0_ENABLE_INSTRUCTION_CACHE | \
610 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
Scott Wood96b8a052007-04-16 14:54:15 -0500611
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200612#define CONFIG_SYS_HID2 HID2_HBE
Scott Wood96b8a052007-04-16 14:54:15 -0500613
Becky Bruce31d82672008-05-08 19:02:12 -0500614#define CONFIG_HIGH_BATS 1 /* High BATs supported */
615
Scott Wood96b8a052007-04-16 14:54:15 -0500616/* DDR @ 0x00000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500617#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
Joe Hershberger261c07b2011-10-11 23:57:10 -0500618#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
619 | BATU_BL_256M \
620 | BATU_VS \
621 | BATU_VP)
Scott Wood96b8a052007-04-16 14:54:15 -0500622
623/* PCI @ 0x80000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500624#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
Joe Hershberger261c07b2011-10-11 23:57:10 -0500625#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
626 | BATU_BL_256M \
627 | BATU_VS \
628 | BATU_VP)
629#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500630 | BATL_PP_RW \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500631 | BATL_CACHEINHIBIT \
632 | BATL_GUARDEDSTORAGE)
633#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
634 | BATU_BL_256M \
635 | BATU_VS \
636 | BATU_VP)
Scott Wood96b8a052007-04-16 14:54:15 -0500637
638/* PCI2 not supported on 8313 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200639#define CONFIG_SYS_IBAT3L (0)
640#define CONFIG_SYS_IBAT3U (0)
641#define CONFIG_SYS_IBAT4L (0)
642#define CONFIG_SYS_IBAT4U (0)
Scott Wood96b8a052007-04-16 14:54:15 -0500643
644/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500645#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500646 | BATL_PP_RW \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500647 | BATL_CACHEINHIBIT \
648 | BATL_GUARDEDSTORAGE)
649#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
650 | BATU_BL_256M \
651 | BATU_VS \
652 | BATU_VP)
Scott Wood96b8a052007-04-16 14:54:15 -0500653
654/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500655#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200656#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Scott Wood96b8a052007-04-16 14:54:15 -0500657
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200658#define CONFIG_SYS_IBAT7L (0)
659#define CONFIG_SYS_IBAT7U (0)
Scott Wood96b8a052007-04-16 14:54:15 -0500660
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200661#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
662#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
663#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
664#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
665#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
666#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
667#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
668#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
669#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
670#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
671#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
672#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
673#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
674#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
675#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
676#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Scott Wood96b8a052007-04-16 14:54:15 -0500677
678/*
Scott Wood96b8a052007-04-16 14:54:15 -0500679 * Environment Configuration
680 */
681#define CONFIG_ENV_OVERWRITE
682
Joe Hershberger261c07b2011-10-11 23:57:10 -0500683#define CONFIG_NETDEV "eth1"
Scott Wood96b8a052007-04-16 14:54:15 -0500684
685#define CONFIG_HOSTNAME mpc8313erdb
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000686#define CONFIG_ROOTPATH "/nfs/root/path"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000687#define CONFIG_BOOTFILE "uImage"
Joe Hershberger261c07b2011-10-11 23:57:10 -0500688 /* U-Boot image on TFTP server */
689#define CONFIG_UBOOTPATH "u-boot.bin"
690#define CONFIG_FDTFILE "mpc8313erdb.dtb"
Scott Wood96b8a052007-04-16 14:54:15 -0500691
Joe Hershberger261c07b2011-10-11 23:57:10 -0500692 /* default location for tftp and bootm */
693#define CONFIG_LOADADDR 800000
Kim Phillips7fd0bea2008-09-24 08:46:25 -0500694#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Scott Wood96b8a052007-04-16 14:54:15 -0500695#define CONFIG_BAUDRATE 115200
696
Scott Wood96b8a052007-04-16 14:54:15 -0500697#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500698 "netdev=" CONFIG_NETDEV "\0" \
Scott Wood96b8a052007-04-16 14:54:15 -0500699 "ethprime=TSEC1\0" \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500700 "uboot=" CONFIG_UBOOTPATH "\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200701 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut5368c552012-09-23 17:41:24 +0200702 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
703 " +$filesize; " \
704 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
705 " +$filesize; " \
706 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
707 " $filesize; " \
708 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
709 " +$filesize; " \
710 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
711 " $filesize\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500712 "fdtaddr=780000\0" \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500713 "fdtfile=" CONFIG_FDTFILE "\0" \
Scott Wood96b8a052007-04-16 14:54:15 -0500714 "console=ttyS0\0" \
715 "setbootargs=setenv bootargs " \
716 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200717 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500718 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
719 "$netdev:off " \
Scott Wood96b8a052007-04-16 14:54:15 -0500720 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
721
722#define CONFIG_NFSBOOTCOMMAND \
723 "setenv rootdev /dev/nfs;" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200724 "run setbootargs;" \
725 "run setipargs;" \
Scott Wood96b8a052007-04-16 14:54:15 -0500726 "tftp $loadaddr $bootfile;" \
727 "tftp $fdtaddr $fdtfile;" \
728 "bootm $loadaddr - $fdtaddr"
729
730#define CONFIG_RAMBOOTCOMMAND \
731 "setenv rootdev /dev/ram;" \
732 "run setbootargs;" \
733 "tftp $ramdiskaddr $ramdiskfile;" \
734 "tftp $loadaddr $bootfile;" \
735 "tftp $fdtaddr $fdtfile;" \
736 "bootm $loadaddr $ramdiskaddr $fdtaddr"
737
Scott Wood96b8a052007-04-16 14:54:15 -0500738#endif /* __CONFIG_H */