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Wolfgang Denk6ccec442006-10-24 14:42:37 +02001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * Configuration settings for the ATSTK1002 CPU daughterboard
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
Andreas Bießmann5d73bc72010-11-04 23:15:30 +000027#include <asm/arch/hardware.h>
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020028
Andreas Bießmanne3e8d462011-04-18 04:12:36 +000029#define CONFIG_AVR32
30#define CONFIG_AT32AP
31#define CONFIG_AT32AP7000
32#define CONFIG_ATSTK1002
33#define CONFIG_ATSTK1000
Wolfgang Denk6ccec442006-10-24 14:42:37 +020034
Wolfgang Denk6ccec442006-10-24 14:42:37 +020035/*
36 * Timer clock frequency. We're using the CPU-internal COUNT register
37 * for this, so this is equivalent to the CPU core clock frequency
38 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_HZ 1000
Wolfgang Denk6ccec442006-10-24 14:42:37 +020040
41/*
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020042 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
43 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
44 * PLL frequency.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
Wolfgang Denk6ccec442006-10-24 14:42:37 +020046 */
Andreas Bießmanne3e8d462011-04-18 04:12:36 +000047#define CONFIG_PLL
48#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_OSC0_HZ 20000000
50#define CONFIG_SYS_PLL0_DIV 1
51#define CONFIG_SYS_PLL0_MUL 7
52#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020053/*
54 * Set the CPU running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020056 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_CLKDIV_CPU 0
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020058/*
59 * Set the HSB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020061 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_CLKDIV_HSB 1
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020063/*
64 * Set the PBA running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020066 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_CLKDIV_PBA 2
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020068/*
69 * Set the PBB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020071 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_CLKDIV_PBB 1
Wolfgang Denk6ccec442006-10-24 14:42:37 +020073
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070074/* Reserve VM regions for SDRAM and NOR flash */
75#define CONFIG_SYS_NR_VM_REGIONS 2
76
Wolfgang Denk6ccec442006-10-24 14:42:37 +020077/*
78 * The PLLOPT register controls the PLL like this:
79 * icp = PLLOPT<2>
80 * ivco = PLLOPT<1:0>
81 *
82 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
83 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_PLL0_OPT 0x04
Wolfgang Denk6ccec442006-10-24 14:42:37 +020085
Andreas Bießmannf4278b72010-11-04 23:15:31 +000086#define CONFIG_USART_BASE ATMEL_BASE_USART1
87#define CONFIG_USART_ID 1
Wolfgang Denk6ccec442006-10-24 14:42:37 +020088
89/* User serviceable stuff */
Andreas Bießmanne3e8d462011-04-18 04:12:36 +000090#define CONFIG_DOS_PARTITION
Haavard Skinnemoen8e687512006-12-17 18:56:46 +010091
Andreas Bießmanne3e8d462011-04-18 04:12:36 +000092#define CONFIG_CMDLINE_TAG
93#define CONFIG_SETUP_MEMORY_TAGS
94#define CONFIG_INITRD_TAG
Wolfgang Denk6ccec442006-10-24 14:42:37 +020095
96#define CONFIG_STACKSIZE (2048)
97
98#define CONFIG_BAUDRATE 115200
99#define CONFIG_BOOTARGS \
Eirik Aanonsene80e5852007-09-18 08:47:20 +0200100 "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
Haavard Skinnemoen1b804b22007-03-21 19:47:36 +0100101
102#define CONFIG_BOOTCOMMAND \
103 "fsload; bootm $(fileaddr)"
104
105/*
106 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
107 * data on the serial line may interrupt the boot sequence.
108 */
Hans-Christian Egtvedt696dd132007-08-30 15:03:05 +0200109#define CONFIG_BOOTDELAY 1
Andreas Bießmanne3e8d462011-04-18 04:12:36 +0000110#define CONFIG_AUTOBOOT
111#define CONFIG_AUTOBOOT_KEYED
Wolfgang Denkc37207d2008-07-16 16:38:59 +0200112#define CONFIG_AUTOBOOT_PROMPT \
113 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Haavard Skinnemoen1b804b22007-03-21 19:47:36 +0100114#define CONFIG_AUTOBOOT_DELAY_STR "d"
115#define CONFIG_AUTOBOOT_STOP_STR " "
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200116
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +0100117/*
Haavard Skinnemoen8b6684a2007-10-24 15:48:37 +0200118 * After booting the board for the first time, new ethernet addresses
119 * should be generated and assigned to the environment variables
120 * "ethaddr" and "eth1addr". This is normally done during production.
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +0100121 */
Andreas Bießmanne3e8d462011-04-18 04:12:36 +0000122#define CONFIG_OVERWRITE_ETHADDR_ONCE
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +0100123
Jon Loeliger2fd90ce2007-07-09 21:48:26 -0500124/*
125 * BOOTP options
126 */
127#define CONFIG_BOOTP_SUBNETMASK
128#define CONFIG_BOOTP_GATEWAY
129
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200130
Jon Loeliger0b361c92007-07-04 22:31:42 -0500131/*
132 * Command line configuration.
133 */
134#include <config_cmd_default.h>
135
136#define CONFIG_CMD_ASKENV
137#define CONFIG_CMD_DHCP
138#define CONFIG_CMD_EXT2
139#define CONFIG_CMD_FAT
140#define CONFIG_CMD_JFFS2
141#define CONFIG_CMD_MMC
Jon Loeliger0b361c92007-07-04 22:31:42 -0500142
David Brownell55ac7a72008-02-22 12:54:39 -0800143#undef CONFIG_CMD_FPGA
Jon Loeliger0b361c92007-07-04 22:31:42 -0500144#undef CONFIG_CMD_SETGETDCR
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200145#undef CONFIG_CMD_SOURCE
Jon Loeliger0b361c92007-07-04 22:31:42 -0500146#undef CONFIG_CMD_XIMG
147
Andreas Bießmanne3e8d462011-04-18 04:12:36 +0000148#define CONFIG_ATMEL_USART
149#define CONFIG_MACB
150#define CONFIG_PORTMUX_PIO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_NR_PIOS 5
Andreas Bießmanne3e8d462011-04-18 04:12:36 +0000152#define CONFIG_SYS_HSDRAMC
153#define CONFIG_MMC
Sven Schnelle72fa4672011-10-21 14:49:25 +0200154#define CONFIG_GENERIC_ATMEL_MCI
155#define CONFIG_GENERIC_MMC
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_DCACHE_LINESZ 32
158#define CONFIG_SYS_ICACHE_LINESZ 32
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200159
160#define CONFIG_NR_DRAM_BANKS 1
161
Andreas Bießmann22178652011-06-28 04:15:58 +0000162#define CONFIG_SYS_FLASH_CFI
163#define CONFIG_FLASH_CFI_DRIVER
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_FLASH_BASE 0x00000000
166#define CONFIG_SYS_FLASH_SIZE 0x800000
167#define CONFIG_SYS_MAX_FLASH_BANKS 1
168#define CONFIG_SYS_MAX_FLASH_SECT 135
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann47293c12011-04-18 04:12:44 +0000171#define CONFIG_SYS_TEXT_BASE 0x00000000
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
174#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
175#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200176
Andreas Bießmanne3e8d462011-04-18 04:12:36 +0000177#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200178#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_MALLOC_LEN (256*1024)
184#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
Haavard Skinnemoen1f4f2122006-11-20 15:53:10 +0100185
Haavard Skinnemoen8269ab52007-11-22 17:01:24 +0100186/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
188#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200189
190/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_PROMPT "U-Boot> "
192#define CONFIG_SYS_CBSIZE 256
193#define CONFIG_SYS_MAXARGS 16
194#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmanne3e8d462011-04-18 04:12:36 +0000195#define CONFIG_SYS_LONGHELP
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
198#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
199#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200200
201#endif /* __CONFIG_H */