blob: 8f9535a4dbc0cca22355d2aa525bd5ff47e43ae5 [file] [log] [blame]
Tom Rini4549e782018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay3d2d1152018-03-12 10:46:17 +01002/*
3 * Copyright : STMicroelectronics 2018
Patrick Delaunay3d2d1152018-03-12 10:46:17 +01004 */
5
6/ {
7 aliases {
8 gpio0 = &gpioa;
9 gpio1 = &gpiob;
10 gpio2 = &gpioc;
11 gpio3 = &gpiod;
12 gpio4 = &gpioe;
13 gpio5 = &gpiof;
14 gpio6 = &gpiog;
15 gpio7 = &gpioh;
16 gpio8 = &gpioi;
17 gpio9 = &gpioj;
18 gpio10 = &gpiok;
19 gpio25 = &gpioz;
Patrick Delaunay1258e462019-04-12 14:38:28 +020020 pinctrl0 = &pinctrl;
21 pinctrl1 = &pinctrl_z;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010022 };
23
Patrick Delaunay35a54d42019-07-11 11:15:28 +020024 clocks {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010025 u-boot,dm-pre-reloc;
26 };
27
Patrick Delaunay67b76842019-07-30 19:16:15 +020028 /* need PSCI for sysreset during board_f */
29 psci {
30 u-boot,dm-pre-proper;
31 };
32
Patrick Delaunay35a54d42019-07-11 11:15:28 +020033 reboot {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010034 u-boot,dm-pre-reloc;
35 };
36
37 soc {
38 u-boot,dm-pre-reloc;
Patrick Delaunaye16750f2018-03-20 11:45:14 +010039 };
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010040};
41
Patrick Delaunaybfe1f082019-02-27 17:01:27 +010042&bsec {
Patrick Delaunay35a54d42019-07-11 11:15:28 +020043 u-boot,dm-pre-proper;
44};
45
46&clk_csi {
Patrick Delaunaybfe1f082019-02-27 17:01:27 +010047 u-boot,dm-pre-reloc;
48};
49
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010050&clk_hsi {
51 u-boot,dm-pre-reloc;
52};
53
54&clk_hse {
55 u-boot,dm-pre-reloc;
56};
57
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010058&clk_lsi {
59 u-boot,dm-pre-reloc;
60};
61
Patrick Delaunay35a54d42019-07-11 11:15:28 +020062&clk_lse {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010063 u-boot,dm-pre-reloc;
64};
65
66&gpioa {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010067 u-boot,dm-pre-reloc;
68};
69
70&gpiob {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010071 u-boot,dm-pre-reloc;
72};
73
74&gpioc {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010075 u-boot,dm-pre-reloc;
76};
77
78&gpiod {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010079 u-boot,dm-pre-reloc;
80};
81
82&gpioe {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010083 u-boot,dm-pre-reloc;
84};
85
86&gpiof {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010087 u-boot,dm-pre-reloc;
88};
89
90&gpiog {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010091 u-boot,dm-pre-reloc;
92};
93
94&gpioh {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010095 u-boot,dm-pre-reloc;
96};
97
98&gpioi {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010099 u-boot,dm-pre-reloc;
100};
101
102&gpioj {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100103 u-boot,dm-pre-reloc;
104};
105
106&gpiok {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100107 u-boot,dm-pre-reloc;
108};
109
110&gpioz {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100111 u-boot,dm-pre-reloc;
112};
Patrice Chotard75500a42019-04-30 17:26:21 +0200113
Patrick Delaunay6d923002019-07-30 19:16:14 +0200114&iwdg2 {
115 u-boot,dm-pre-reloc;
116};
117
Patrick Delaunay2c258092019-07-30 19:16:16 +0200118/* pre-reloc probe = reserve video frame buffer in video_reserve() */
119&ltdc {
120 u-boot,dm-pre-proper;
121};
122
Patrick Delaunay35a54d42019-07-11 11:15:28 +0200123&pinctrl {
Patrice Chotard75500a42019-04-30 17:26:21 +0200124 u-boot,dm-pre-reloc;
125};
Patrick Delaunay35a54d42019-07-11 11:15:28 +0200126
127&pinctrl_z {
128 u-boot,dm-pre-reloc;
129};
130
Patrick Delaunay7915b992020-01-28 10:10:59 +0100131&pwr_regulators {
Patrick Delaunay35a54d42019-07-11 11:15:28 +0200132 u-boot,dm-pre-reloc;
133};
134
135&rcc {
136 u-boot,dm-pre-reloc;
Patrick Delaunay8d93a972020-01-28 10:11:03 +0100137 #address-cells = <1>;
138 #size-cells = <0>;
Patrick Delaunay35a54d42019-07-11 11:15:28 +0200139};
140
141&sdmmc1 {
142 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
143};
144
145&sdmmc2 {
146 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
147};
148
149&sdmmc3 {
150 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
151};
152
153&usbotg_hs {
154 compatible = "st,stm32mp1-hsotg", "snps,dwc2";
155};