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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roesedd580802014-10-22 12:13:18 +02002/*
Stefan Roesec4be10b2015-12-03 12:39:45 +01003 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
Stefan Roesedd580802014-10-22 12:13:18 +02004 */
5
6#ifndef _CONFIG_DB_MV7846MP_GP_H
7#define _CONFIG_DB_MV7846MP_GP_H
8
9/*
10 * High Level Configuration Options (easy to change)
11 */
Stefan Roese25541672015-01-19 11:33:46 +010012#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
13
Stefan Roese2923c2d2015-08-06 14:27:36 +020014/*
15 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
16 * for DDR ECC byte filling in the SPL before loading the main
17 * U-Boot into it.
18 */
Stefan Roesedd580802014-10-22 12:13:18 +020019#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
20
Stefan Roesedd580802014-10-22 12:13:18 +020021/* I2C */
22#define CONFIG_SYS_I2C
23#define CONFIG_SYS_I2C_MVTWSI
Paul Kocialkowskidd822422015-04-10 23:09:51 +020024#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roesedd580802014-10-22 12:13:18 +020025#define CONFIG_SYS_I2C_SLAVE 0x0
26#define CONFIG_SYS_I2C_SPEED 100000
27
Stefan Roese49114c82015-07-22 18:05:43 +020028/* USB/EHCI configuration */
Stefan Roese49114c82015-07-22 18:05:43 +020029#define CONFIG_EHCI_IS_TDI
Anton Schubert8a333712015-07-23 15:02:09 +020030#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
Stefan Roese49114c82015-07-22 18:05:43 +020031
Stefan Roesedd580802014-10-22 12:13:18 +020032/* Environment in SPI NOR flash */
Stefan Roesedd580802014-10-22 12:13:18 +020033#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
34#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
35#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
36
Stefan Roesedd580802014-10-22 12:13:18 +020037#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
Stefan Roesedd580802014-10-22 12:13:18 +020038
Anton Schuberte863f7f2015-07-15 14:50:05 +020039/* SATA support */
Stefan Roesec4be10b2015-12-03 12:39:45 +010040#define CONFIG_SYS_SATA_MAX_DEVICE 2
Stefan Roesec4be10b2015-12-03 12:39:45 +010041#define CONFIG_LBA48
Anton Schuberte863f7f2015-07-15 14:50:05 +020042
Stefan Roese41e705a2015-08-11 09:36:15 +020043/* PCIe support */
Stefan Roese64512232015-11-25 07:37:00 +010044#ifndef CONFIG_SPL_BUILD
Stefan Roese41e705a2015-08-11 09:36:15 +020045#define CONFIG_PCI_SCAN_SHOW
Stefan Roese64512232015-11-25 07:37:00 +010046#endif
Stefan Roese41e705a2015-08-11 09:36:15 +020047
Stefan Roesed6b63032015-07-23 10:26:18 +020048/* NAND */
49#define CONFIG_SYS_NAND_USE_FLASH_BBT
50#define CONFIG_SYS_NAND_ONFI_DETECTION
51
Stefan Roesedd580802014-10-22 12:13:18 +020052/*
53 * mv-common.h should be defined after CMD configs since it used them
54 * to enable certain macros
55 */
56#include "mv-common.h"
57
Stefan Roese25541672015-01-19 11:33:46 +010058/*
59 * Memory layout while starting into the bin_hdr via the
60 * BootROM:
61 *
62 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
63 * 0x4000.4030 bin_hdr start address
64 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
65 * 0x4007.fffc BootROM stack top
66 *
67 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
68 * L2 cache thus cannot be used.
69 */
70
71/* SPL */
72/* Defines for SPL */
Stefan Roese25541672015-01-19 11:33:46 +010073#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
74
75#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
76#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
77
Stefan Roese64512232015-11-25 07:37:00 +010078#ifdef CONFIG_SPL_BUILD
79#define CONFIG_SYS_MALLOC_SIMPLE
80#endif
Stefan Roese25541672015-01-19 11:33:46 +010081
82#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
83#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
84
Stefan Roese25541672015-01-19 11:33:46 +010085/* SPL related SPI defines */
Stefan Roese25541672015-01-19 11:33:46 +010086#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
Stefan Roese2bd87112015-08-03 12:13:09 +020087#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
Stefan Roese25541672015-01-19 11:33:46 +010088
89/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
Stefan Roese25541672015-01-19 11:33:46 +010090#define CONFIG_SPD_EEPROM 0x4e
Stefan Roese698ffab2015-12-10 15:02:38 +010091#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
Stefan Roese25541672015-01-19 11:33:46 +010092
Stefan Roesedd580802014-10-22 12:13:18 +020093#endif /* _CONFIG_DB_MV7846MP_GP_H */