blob: 322adb530a343a096e695dfdb8f449d82a565da6 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ashish Kumare84a3242017-08-31 16:12:54 +05302/*
3 * Copyright 2017 NXP
Ashish Kumare84a3242017-08-31 16:12:54 +05304 */
5
6#ifndef __LS1088A_RDB_H
7#define __LS1088A_RDB_H
8
9#include "ls1088a_common.h"
10
Pankit Garg143af3c2018-12-27 04:37:55 +000011#ifdef CONFIG_TFABOOT
12#define CONFIG_SYS_MMC_ENV_DEV 0
13
14#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
15#define CONFIG_ENV_OFFSET 0x500000
16#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
17 CONFIG_ENV_OFFSET)
18#define CONFIG_ENV_SECT_SIZE 0x40000
19#else
Ashish Kumare84a3242017-08-31 16:12:54 +053020#if defined(CONFIG_QSPI_BOOT)
Ashish Kumare84a3242017-08-31 16:12:54 +053021#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
Ashish Kumare84a3242017-08-31 16:12:54 +053022#define CONFIG_ENV_SECT_SIZE 0x40000
Ashish Kumar099f4092017-11-06 13:18:43 +053023#elif defined(CONFIG_SD_BOOT)
24#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
25#define CONFIG_SYS_MMC_ENV_DEV 0
26#define CONFIG_ENV_SIZE 0x2000
Ashish Kumare84a3242017-08-31 16:12:54 +053027#else
28#define CONFIG_ENV_IS_IN_FLASH
29#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
30#define CONFIG_ENV_SECT_SIZE 0x20000
31#define CONFIG_ENV_SIZE 0x20000
32#endif
Pankit Garg143af3c2018-12-27 04:37:55 +000033#endif /* CONFIG_TFABOOT */
Ashish Kumare84a3242017-08-31 16:12:54 +053034
Pankit Garg143af3c2018-12-27 04:37:55 +000035#if defined(CONFIG_TFABOOT) || \
36 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Sumit Garg10e7eaf2018-01-06 09:04:24 +053037#ifndef CONFIG_SPL_BUILD
Ashish Kumare84a3242017-08-31 16:12:54 +053038#define CONFIG_QIXIS_I2C_ACCESS
Sumit Garg10e7eaf2018-01-06 09:04:24 +053039#endif
Ashish Kumare84a3242017-08-31 16:12:54 +053040#define SYS_NO_FLASH
Ashish Kumar099f4092017-11-06 13:18:43 +053041#undef CONFIG_CMD_IMLS
Ashish Kumare84a3242017-08-31 16:12:54 +053042#endif
43
44#define CONFIG_SYS_CLK_FREQ 100000000
45#define CONFIG_DDR_CLK_FREQ 100000000
46#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
47#define COUNTER_FREQUENCY 25000000 /* 25MHz */
48
49#define CONFIG_DDR_SPD
50#ifdef CONFIG_EMU
51#define CONFIG_SYS_FSL_DDR_EMU
52#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
53#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
54#else
55#define CONFIG_DDR_ECC
56#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
57#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
58#endif
59#define SPD_EEPROM_ADDRESS 0x51
60#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
61#define CONFIG_DIMM_SLOTS_PER_CTLR 1
62
63
64#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
65#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
66#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
67#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
68
69#define CONFIG_SYS_NOR0_CSPR \
70 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
71 CSPR_PORT_SIZE_16 | \
72 CSPR_MSEL_NOR | \
73 CSPR_V)
74#define CONFIG_SYS_NOR0_CSPR_EARLY \
75 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
76 CSPR_PORT_SIZE_16 | \
77 CSPR_MSEL_NOR | \
78 CSPR_V)
79#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
80#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
81 FTIM0_NOR_TEADC(0x1) | \
82 FTIM0_NOR_TEAHC(0x1))
83#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
84 FTIM1_NOR_TRAD_NOR(0x1))
85#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
86 FTIM2_NOR_TCH(0x0) | \
87 FTIM2_NOR_TWP(0x1))
88#define CONFIG_SYS_NOR_FTIM3 0x04000000
89#define CONFIG_SYS_IFC_CCR 0x01000000
90
91#ifndef SYS_NO_FLASH
Ashish Kumare84a3242017-08-31 16:12:54 +053092#define CONFIG_SYS_FLASH_QUIET_TEST
93#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
94
95#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
96#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
97#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
98#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
99
100#define CONFIG_SYS_FLASH_EMPTY_INFO
101#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
102#endif
103#endif
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530104
105#ifndef SPL_NO_IFC
Ashish Kumard798a6e2017-11-28 10:52:17 +0530106#define CONFIG_NAND_FSL_IFC
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530107#endif
108
Ashish Kumare84a3242017-08-31 16:12:54 +0530109#define CONFIG_SYS_NAND_MAX_ECCPOS 256
110#define CONFIG_SYS_NAND_MAX_OOBFREE 2
111
112#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
113#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
114 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
115 | CSPR_MSEL_NAND /* MSEL = NAND */ \
116 | CSPR_V)
117#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
118
119#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
120 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
121 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
122 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
123 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
124 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
125 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
126
127#define CONFIG_SYS_NAND_ONFI_DETECTION
128
129/* ONFI NAND Flash mode0 Timing Params */
130#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
131 FTIM0_NAND_TWP(0x18) | \
132 FTIM0_NAND_TWCHT(0x07) | \
133 FTIM0_NAND_TWH(0x0a))
134#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
135 FTIM1_NAND_TWBE(0x39) | \
136 FTIM1_NAND_TRR(0x0e) | \
137 FTIM1_NAND_TRP(0x18))
138#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
139 FTIM2_NAND_TREH(0x0a) | \
140 FTIM2_NAND_TWHRE(0x1e))
141#define CONFIG_SYS_NAND_FTIM3 0x0
142
143#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
144#define CONFIG_SYS_MAX_NAND_DEVICE 1
145#define CONFIG_MTD_NAND_VERIFY_WRITE
Ashish Kumard798a6e2017-11-28 10:52:17 +0530146#define CONFIG_CMD_NAND
Ashish Kumare84a3242017-08-31 16:12:54 +0530147
148#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
149
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530150#ifndef SPL_NO_QIXIS
Ashish Kumare84a3242017-08-31 16:12:54 +0530151#define CONFIG_FSL_QIXIS
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530152#endif
153
Ashish Kumare84a3242017-08-31 16:12:54 +0530154#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
Rajesh Bhagatef0789b2018-01-17 16:13:09 +0530155#define QIXIS_BRDCFG4_OFFSET 0x54
Ashish Kumare84a3242017-08-31 16:12:54 +0530156#define QIXIS_LBMAP_SWITCH 2
157#define QIXIS_QMAP_MASK 0xe0
158#define QIXIS_QMAP_SHIFT 5
159#define QIXIS_LBMAP_MASK 0x1f
160#define QIXIS_LBMAP_SHIFT 5
161#define QIXIS_LBMAP_DFLTBANK 0x00
162#define QIXIS_LBMAP_ALTBANK 0x20
163#define QIXIS_LBMAP_SD 0x00
Ashish Kumar6c8945e2018-01-17 12:16:37 +0530164#define QIXIS_LBMAP_EMMC 0x00
Ashish Kumare84a3242017-08-31 16:12:54 +0530165#define QIXIS_LBMAP_SD_QSPI 0x00
166#define QIXIS_LBMAP_QSPI 0x00
167#define QIXIS_RCW_SRC_SD 0x40
Ashish Kumar6c8945e2018-01-17 12:16:37 +0530168#define QIXIS_RCW_SRC_EMMC 0x41
Ashish Kumare84a3242017-08-31 16:12:54 +0530169#define QIXIS_RCW_SRC_QSPI 0x62
170#define QIXIS_RST_CTL_RESET 0x31
171#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
172#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
173#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
174#define QIXIS_RST_FORCE_MEM 0x01
175
176#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
177#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
178 | CSPR_PORT_SIZE_8 \
179 | CSPR_MSEL_GPCM \
180 | CSPR_V)
181#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
182 | CSPR_PORT_SIZE_8 \
183 | CSPR_MSEL_GPCM \
184 | CSPR_V)
185
186#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
187#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
188/* QIXIS Timing parameters*/
189#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
190 FTIM0_GPCM_TEADC(0x0e) | \
191 FTIM0_GPCM_TEAHC(0x0e))
192#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
193 FTIM1_GPCM_TRAD(0x3f))
194#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
195 FTIM2_GPCM_TCH(0xf) | \
196 FTIM2_GPCM_TWP(0x3E))
197#define SYS_FPGA_CS_FTIM3 0x0
198
Pankit Garg143af3c2018-12-27 04:37:55 +0000199#if defined(CONFIG_TFABOOT) || \
200 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Ashish Kumare84a3242017-08-31 16:12:54 +0530201#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
202#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
203#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
204#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
205#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
206#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
207#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
208#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
209#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
210#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
211#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
212#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
213#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
214#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
215#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
216#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
217#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
218#else
219#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
220#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
221#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
222#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
223#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
224#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
225#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
226#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
227#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
228#endif
229
Ashish Kumare84a3242017-08-31 16:12:54 +0530230#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
231
Rajesh Bhagat23a12cb2018-01-17 16:13:05 +0530232#define I2C_MUX_CH_VOL_MONITOR 0xA
233/* Voltage monitor on channel 2*/
234#define I2C_VOL_MONITOR_ADDR 0x63
235#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
236#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
237#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
Rajesh Bhagatef0789b2018-01-17 16:13:09 +0530238#define I2C_SVDD_MONITOR_ADDR 0x4F
239
240#define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
241#define CONFIG_VID
242
243/* The lowest and highest voltage allowed for LS1088ARDB */
244#define VDD_MV_MIN 819
245#define VDD_MV_MAX 1212
246
247#define CONFIG_VOL_MONITOR_LTC3882_SET
248#define CONFIG_VOL_MONITOR_LTC3882_READ
Rajesh Bhagat23a12cb2018-01-17 16:13:05 +0530249
250/* PM Bus commands code for LTC3882*/
251#define PMBUS_CMD_PAGE 0x0
252#define PMBUS_CMD_READ_VOUT 0x8B
253#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
254#define PMBUS_CMD_VOUT_COMMAND 0x21
255
256#define PWM_CHANNEL0 0x0
257
Ashish Kumare84a3242017-08-31 16:12:54 +0530258/*
259 * I2C bus multiplexer
260 */
261#define I2C_MUX_PCA_ADDR_PRI 0x77
262#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
263#define I2C_RETIMER_ADDR 0x18
264#define I2C_MUX_CH_DEFAULT 0x8
265#define I2C_MUX_CH5 0xD
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530266
267#ifndef SPL_NO_RTC
Ashish Kumare84a3242017-08-31 16:12:54 +0530268/*
269* RTC configuration
270*/
271#define RTC
272#define CONFIG_RTC_PCF8563 1
273#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
274#define CONFIG_CMD_DATE
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530275#endif
Ashish Kumare84a3242017-08-31 16:12:54 +0530276
277/* EEPROM */
278#define CONFIG_ID_EEPROM
279#define CONFIG_SYS_I2C_EEPROM_NXID
280#define CONFIG_SYS_EEPROM_BUS_NUM 0
281#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
282#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
283#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
284#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
285
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530286#ifndef SPL_NO_QSPI
Ashish Kumare84a3242017-08-31 16:12:54 +0530287/* QSPI device */
Pankit Garg143af3c2018-12-27 04:37:55 +0000288#if defined(CONFIG_TFABOOT) || \
289 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Ashish Kumare84a3242017-08-31 16:12:54 +0530290#define FSL_QSPI_FLASH_SIZE (1 << 26)
291#define FSL_QSPI_FLASH_NUM 2
292#endif
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530293#endif
Ashish Kumare84a3242017-08-31 16:12:54 +0530294
295#define CONFIG_CMD_MEMINFO
Ashish Kumare84a3242017-08-31 16:12:54 +0530296#define CONFIG_SYS_MEMTEST_START 0x80000000
297#define CONFIG_SYS_MEMTEST_END 0x9fffffff
298
Ashish Kumar099f4092017-11-06 13:18:43 +0530299#ifdef CONFIG_SPL_BUILD
300#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
301#else
Ashish Kumare84a3242017-08-31 16:12:54 +0530302#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Ashish Kumar099f4092017-11-06 13:18:43 +0530303#endif
Ashish Kumare84a3242017-08-31 16:12:54 +0530304
305#define CONFIG_FSL_MEMAC
306
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530307#ifndef SPL_NO_ENV
Ashish Kumare84a3242017-08-31 16:12:54 +0530308/* Initial environment variables */
Pankit Garg143af3c2018-12-27 04:37:55 +0000309#ifdef CONFIG_TFABOOT
310#define QSPI_MC_INIT_CMD \
311 "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
312 "sf read 0x80100000 0xE00000 0x100000;" \
313 "env exists secureboot && " \
314 "sf read 0x80700000 0x700000 0x40000 && " \
315 "sf read 0x80740000 0x740000 0x40000 && " \
316 "esbc_validate 0x80700000 && " \
317 "esbc_validate 0x80740000 ;" \
318 "fsl_mc start mc 0x80000000 0x80100000\0"
319#define SD_MC_INIT_CMD \
320 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
321 "mmc read 0x80100000 0x7000 0x800;" \
322 "env exists secureboot && " \
323 "mmc read 0x80700000 0x3800 0x10 && " \
324 "mmc read 0x80740000 0x3A00 0x10 && " \
325 "esbc_validate 0x80700000 && " \
326 "esbc_validate 0x80740000 ;" \
327 "fsl_mc start mc 0x80000000 0x80100000\0"
328#else
Ashish Kumare84a3242017-08-31 16:12:54 +0530329#if defined(CONFIG_QSPI_BOOT)
Ashish Kumard9195c62017-11-06 13:19:28 +0530330#define MC_INIT_CMD \
Ashish Kumare84a3242017-08-31 16:12:54 +0530331 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530332 "sf read 0x80100000 0xE00000 0x100000;" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530333 "env exists secureboot && " \
334 "sf read 0x80700000 0x700000 0x40000 && " \
335 "sf read 0x80740000 0x740000 0x40000 && " \
336 "esbc_validate 0x80700000 && " \
337 "esbc_validate 0x80740000 ;" \
338 "fsl_mc start mc 0x80000000 0x80100000\0" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530339 "mcmemsize=0x70000000\0"
Ashish Kumar099f4092017-11-06 13:18:43 +0530340#elif defined(CONFIG_SD_BOOT)
Ashish Kumard9195c62017-11-06 13:19:28 +0530341#define MC_INIT_CMD \
342 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
343 "mmc read 0x80100000 0x7000 0x800;" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530344 "env exists secureboot && " \
345 "mmc read 0x80700000 0x3800 0x10 && " \
346 "mmc read 0x80740000 0x3A00 0x10 && " \
347 "esbc_validate 0x80700000 && " \
348 "esbc_validate 0x80740000 ;" \
349 "fsl_mc start mc 0x80000000 0x80100000\0" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530350 "mcmemsize=0x70000000\0"
351#endif
Pankit Garg143af3c2018-12-27 04:37:55 +0000352#endif /* CONFIG_TFABOOT */
Ashish Kumard9195c62017-11-06 13:19:28 +0530353
Ashish Kumar099f4092017-11-06 13:18:43 +0530354#undef CONFIG_EXTRA_ENV_SETTINGS
Pankit Garg143af3c2018-12-27 04:37:55 +0000355#ifdef CONFIG_TFABOOT
356#define CONFIG_EXTRA_ENV_SETTINGS \
357 "BOARD=ls1088ardb\0" \
358 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
359 "ramdisk_addr=0x800000\0" \
360 "ramdisk_size=0x2000000\0" \
361 "fdt_high=0xa0000000\0" \
362 "initrd_high=0xffffffffffffffff\0" \
363 "fdt_addr=0x64f00000\0" \
364 "kernel_addr=0x1000000\0" \
365 "kernel_addr_sd=0x8000\0" \
366 "kernelhdr_addr_sd=0x4000\0" \
367 "kernel_start=0x580100000\0" \
368 "kernelheader_start=0x580800000\0" \
369 "scriptaddr=0x80000000\0" \
370 "scripthdraddr=0x80080000\0" \
371 "fdtheader_addr_r=0x80100000\0" \
372 "kernelheader_addr=0x800000\0" \
373 "kernelheader_addr_r=0x80200000\0" \
374 "kernel_addr_r=0x81000000\0" \
375 "kernelheader_size=0x40000\0" \
376 "fdt_addr_r=0x90000000\0" \
377 "load_addr=0xa0000000\0" \
378 "kernel_size=0x2800000\0" \
379 "kernel_size_sd=0x14000\0" \
380 "kernelhdr_size_sd=0x10\0" \
381 QSPI_MC_INIT_CMD \
382 "mcmemsize=0x70000000\0" \
383 BOOTENV \
384 "boot_scripts=ls1088ardb_boot.scr\0" \
385 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
386 "scan_dev_for_boot_part=" \
387 "part list ${devtype} ${devnum} devplist; " \
388 "env exists devplist || setenv devplist 1; " \
389 "for distro_bootpart in ${devplist}; do " \
390 "if fstype ${devtype} " \
391 "${devnum}:${distro_bootpart} " \
392 "bootfstype; then " \
393 "run scan_dev_for_boot; " \
394 "fi; " \
395 "done\0" \
Pankit Garg143af3c2018-12-27 04:37:55 +0000396 "boot_a_script=" \
397 "load ${devtype} ${devnum}:${distro_bootpart} " \
398 "${scriptaddr} ${prefix}${script}; " \
399 "env exists secureboot && load ${devtype} " \
400 "${devnum}:${distro_bootpart} " \
Vinitha V Pillai78c58082019-04-23 05:52:17 +0000401 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
402 "env exists secureboot " \
Pankit Garg143af3c2018-12-27 04:37:55 +0000403 "&& esbc_validate ${scripthdraddr};" \
404 "source ${scriptaddr}\0" \
405 "installer=load mmc 0:2 $load_addr " \
406 "/flex_installer_arm64.itb; " \
407 "env exists mcinitcmd && run mcinitcmd && " \
408 "mmc read 0x80001000 0x6800 0x800;" \
409 "fsl_mc lazyapply dpl 0x80001000;" \
410 "bootm $load_addr#ls1088ardb\0" \
411 "qspi_bootcmd=echo Trying load from qspi..;" \
412 "sf probe && sf read $load_addr " \
413 "$kernel_addr $kernel_size ; env exists secureboot " \
414 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
415 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
416 "bootm $load_addr#$BOARD\0" \
417 "sd_bootcmd=echo Trying load from sd card..;" \
418 "mmcinfo; mmc read $load_addr " \
419 "$kernel_addr_sd $kernel_size_sd ;" \
420 "env exists secureboot && mmc read $kernelheader_addr_r "\
421 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
422 " && esbc_validate ${kernelheader_addr_r};" \
423 "bootm $load_addr#$BOARD\0"
424#else
Ashish Kumar099f4092017-11-06 13:18:43 +0530425#define CONFIG_EXTRA_ENV_SETTINGS \
Ashish Kumard9195c62017-11-06 13:19:28 +0530426 "BOARD=ls1088ardb\0" \
Ashish Kumar099f4092017-11-06 13:18:43 +0530427 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
Ashish Kumar099f4092017-11-06 13:18:43 +0530428 "ramdisk_addr=0x800000\0" \
429 "ramdisk_size=0x2000000\0" \
430 "fdt_high=0xa0000000\0" \
431 "initrd_high=0xffffffffffffffff\0" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530432 "fdt_addr=0x64f00000\0" \
433 "kernel_addr=0x1000000\0" \
434 "kernel_addr_sd=0x8000\0" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530435 "kernelhdr_addr_sd=0x4000\0" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530436 "kernel_start=0x580100000\0" \
437 "kernelheader_start=0x580800000\0" \
438 "scriptaddr=0x80000000\0" \
439 "scripthdraddr=0x80080000\0" \
440 "fdtheader_addr_r=0x80100000\0" \
441 "kernelheader_addr=0x800000\0" \
442 "kernelheader_addr_r=0x80200000\0" \
443 "kernel_addr_r=0x81000000\0" \
444 "kernelheader_size=0x40000\0" \
445 "fdt_addr_r=0x90000000\0" \
446 "load_addr=0xa0000000\0" \
447 "kernel_size=0x2800000\0" \
448 "kernel_size_sd=0x14000\0" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530449 "kernelhdr_size_sd=0x10\0" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530450 MC_INIT_CMD \
451 BOOTENV \
452 "boot_scripts=ls1088ardb_boot.scr\0" \
453 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
454 "scan_dev_for_boot_part=" \
455 "part list ${devtype} ${devnum} devplist; " \
456 "env exists devplist || setenv devplist 1; " \
457 "for distro_bootpart in ${devplist}; do " \
458 "if fstype ${devtype} " \
459 "${devnum}:${distro_bootpart} " \
460 "bootfstype; then " \
461 "run scan_dev_for_boot; " \
462 "fi; " \
463 "done\0" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530464 "boot_a_script=" \
465 "load ${devtype} ${devnum}:${distro_bootpart} " \
466 "${scriptaddr} ${prefix}${script}; " \
467 "env exists secureboot && load ${devtype} " \
468 "${devnum}:${distro_bootpart} " \
469 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
470 "&& esbc_validate ${scripthdraddr};" \
471 "source ${scriptaddr}\0" \
472 "installer=load mmc 0:2 $load_addr " \
473 "/flex_installer_arm64.itb; " \
474 "env exists mcinitcmd && run mcinitcmd && " \
Jagdish Gediyaf4ef4762018-06-05 09:04:05 +0530475 "mmc read 0x80001000 0x6800 0x800;" \
476 "fsl_mc lazyapply dpl 0x80001000;" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530477 "bootm $load_addr#ls1088ardb\0" \
478 "qspi_bootcmd=echo Trying load from qspi..;" \
479 "sf probe && sf read $load_addr " \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530480 "$kernel_addr $kernel_size ; env exists secureboot " \
481 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
482 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
Ashish Kumard9195c62017-11-06 13:19:28 +0530483 "bootm $load_addr#$BOARD\0" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530484 "sd_bootcmd=echo Trying load from sd card..;" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530485 "mmcinfo; mmc read $load_addr " \
486 "$kernel_addr_sd $kernel_size_sd ;" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530487 "env exists secureboot && mmc read $kernelheader_addr_r "\
488 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
489 " && esbc_validate ${kernelheader_addr_r};" \
Ashish Kumard9195c62017-11-06 13:19:28 +0530490 "bootm $load_addr#$BOARD\0"
Pankit Garg143af3c2018-12-27 04:37:55 +0000491#endif /* CONFIG_TFABOOT */
Ashish Kumare84a3242017-08-31 16:12:54 +0530492
Ashish Kumard9195c62017-11-06 13:19:28 +0530493#undef CONFIG_BOOTCOMMAND
Pankit Garg143af3c2018-12-27 04:37:55 +0000494#ifdef CONFIG_TFABOOT
495#define QSPI_NOR_BOOTCOMMAND \
496 "sf read 0x80001000 0xd00000 0x100000;" \
497 "env exists mcinitcmd && env exists secureboot " \
498 " && sf read 0x80780000 0x780000 0x100000 " \
499 "&& esbc_validate 0x80780000;env exists mcinitcmd " \
500 "&& fsl_mc lazyapply dpl 0x80001000;" \
501 "run distro_bootcmd;run qspi_bootcmd;" \
502 "env exists secureboot && esbc_halt;"
503#define SD_BOOTCOMMAND \
504 "env exists mcinitcmd && mmcinfo; " \
505 "mmc read 0x80001000 0x6800 0x800; " \
506 "env exists mcinitcmd && env exists secureboot " \
507 " && mmc read 0x80780000 0x3C00 0x10 " \
508 "&& esbc_validate 0x80780000;env exists mcinitcmd " \
509 "&& fsl_mc lazyapply dpl 0x80001000;" \
510 "run distro_bootcmd;run sd_bootcmd;" \
511 "env exists secureboot && esbc_halt;"
512#else
Ashish Kumard9195c62017-11-06 13:19:28 +0530513#if defined(CONFIG_QSPI_BOOT)
514/* Try to boot an on-QSPI kernel first, then do normal distro boot */
515#define CONFIG_BOOTCOMMAND \
Jagdish Gediyaf4ef4762018-06-05 09:04:05 +0530516 "sf read 0x80001000 0xd00000 0x100000;" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530517 "env exists mcinitcmd && env exists secureboot " \
518 " && sf read 0x80780000 0x780000 0x100000 " \
519 "&& esbc_validate 0x80780000;env exists mcinitcmd " \
Jagdish Gediyaf4ef4762018-06-05 09:04:05 +0530520 "&& fsl_mc lazyapply dpl 0x80001000;" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530521 "run distro_bootcmd;run qspi_bootcmd;" \
522 "env exists secureboot && esbc_halt;"
523
Ashish Kumard9195c62017-11-06 13:19:28 +0530524/* Try to boot an on-SD kernel first, then do normal distro boot */
525#elif defined(CONFIG_SD_BOOT)
526#define CONFIG_BOOTCOMMAND \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530527 "env exists mcinitcmd && mmcinfo; " \
Jagdish Gediyaf4ef4762018-06-05 09:04:05 +0530528 "mmc read 0x80001000 0x6800 0x800; " \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530529 "env exists mcinitcmd && env exists secureboot " \
Vinitha V Pillaife6636f2018-06-20 18:59:12 +0530530 " && mmc read 0x80780000 0x3C00 0x10 " \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530531 "&& esbc_validate 0x80780000;env exists mcinitcmd " \
Jagdish Gediyaf4ef4762018-06-05 09:04:05 +0530532 "&& fsl_mc lazyapply dpl 0x80001000;" \
Udit Agarwal30c41d22017-11-22 09:01:26 +0530533 "run distro_bootcmd;run sd_bootcmd;" \
534 "env exists secureboot && esbc_halt;"
Ashish Kumare84a3242017-08-31 16:12:54 +0530535#endif
Pankit Garg143af3c2018-12-27 04:37:55 +0000536#endif /* CONFIG_TFABOOT */
Ashish Kumare84a3242017-08-31 16:12:54 +0530537
538/* MAC/PHY configuration */
539#ifdef CONFIG_FSL_MC_ENET
Ashish Kumare84a3242017-08-31 16:12:54 +0530540#define CONFIG_PHYLIB
541
542#define CONFIG_PHY_VITESSE
Ashish Kumare84a3242017-08-31 16:12:54 +0530543#define AQ_PHY_ADDR1 0x00
544#define AQR105_IRQ_MASK 0x00000004
545
546#define QSGMII1_PORT1_PHY_ADDR 0x0c
547#define QSGMII1_PORT2_PHY_ADDR 0x0d
548#define QSGMII1_PORT3_PHY_ADDR 0x0e
549#define QSGMII1_PORT4_PHY_ADDR 0x0f
550#define QSGMII2_PORT1_PHY_ADDR 0x1c
551#define QSGMII2_PORT2_PHY_ADDR 0x1d
552#define QSGMII2_PORT3_PHY_ADDR 0x1e
553#define QSGMII2_PORT4_PHY_ADDR 0x1f
554
Ashish Kumare84a3242017-08-31 16:12:54 +0530555#define CONFIG_ETHPRIME "DPMAC1@xgmii"
556#define CONFIG_PHY_GIGE
557#endif
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530558#endif
Ashish Kumare84a3242017-08-31 16:12:54 +0530559
560/* MMC */
561#ifdef CONFIG_MMC
Ashish Kumare84a3242017-08-31 16:12:54 +0530562#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
563#endif
564
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530565#ifndef SPL_NO_ENV
Ashish Kumare84a3242017-08-31 16:12:54 +0530566
567#define BOOT_TARGET_DEVICES(func) \
Ashish Kumare84a3242017-08-31 16:12:54 +0530568 func(MMC, mmc, 0) \
Mian Yousaf Kaukab080c9512019-01-29 16:38:32 +0100569 func(SCSI, scsi, 0) \
570 func(DHCP, dhcp, na)
Ashish Kumare84a3242017-08-31 16:12:54 +0530571#include <config_distro_bootcmd.h>
Sumit Garg10e7eaf2018-01-06 09:04:24 +0530572#endif
Ashish Kumare84a3242017-08-31 16:12:54 +0530573
574#include <asm/fsl_secure_boot.h>
575
576#endif /* __LS1088A_RDB_H */