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wdenk507bbe32004-04-18 21:13:41 +00001/*
Michal Simek93768392015-12-01 14:24:20 +01002 * (C) Copyright 2008 - 2015 Michal Simek <monstr@monstr.eu>
Michal Simek53ea9812008-07-11 10:10:31 +02003 * Clean driver and add xilinx constant from header file
wdenk507bbe32004-04-18 21:13:41 +00004 *
Michal Simek53ea9812008-07-11 10:10:31 +02005 * (C) Copyright 2004 Atmark Techno, Inc.
wdenk507bbe32004-04-18 21:13:41 +00006 * Yasushi SHOJI <yashi@atmark-techno.com>
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenk507bbe32004-04-18 21:13:41 +00009 */
10
11#include <config.h>
Michal Simek49a23e42011-09-25 21:03:08 +000012#include <common.h>
Michal Simek93768392015-12-01 14:24:20 +010013#include <dm.h>
Michal Simek53ea9812008-07-11 10:10:31 +020014#include <asm/io.h>
Michal Simek49a23e42011-09-25 21:03:08 +000015#include <linux/compiler.h>
16#include <serial.h>
wdenk507bbe32004-04-18 21:13:41 +000017
Michal Simek93768392015-12-01 14:24:20 +010018DECLARE_GLOBAL_DATA_PTR;
19
20#define SR_TX_FIFO_FULL BIT(3) /* transmit FIFO full */
21#define SR_TX_FIFO_EMPTY BIT(2) /* transmit FIFO empty */
22#define SR_RX_FIFO_VALID_DATA BIT(0) /* data in receive FIFO */
23#define SR_RX_FIFO_FULL BIT(1) /* receive FIFO full */
wdenk507bbe32004-04-18 21:13:41 +000024
Michal Simek8c3bd6b2014-01-21 07:29:47 +010025#define ULITE_CONTROL_RST_TX 0x01
26#define ULITE_CONTROL_RST_RX 0x02
27
Michal Simek49a23e42011-09-25 21:03:08 +000028struct uartlite {
29 unsigned int rx_fifo;
30 unsigned int tx_fifo;
31 unsigned int status;
Michal Simek8c3bd6b2014-01-21 07:29:47 +010032 unsigned int control;
Michal Simek49a23e42011-09-25 21:03:08 +000033};
wdenk507bbe32004-04-18 21:13:41 +000034
Michal Simek93768392015-12-01 14:24:20 +010035struct uartlite_platdata {
36 struct uartlite *regs;
Michal Simek49a23e42011-09-25 21:03:08 +000037};
38
Michal Simek93768392015-12-01 14:24:20 +010039static int uartlite_serial_putc(struct udevice *dev, const char ch)
Michal Simek49a23e42011-09-25 21:03:08 +000040{
Michal Simek93768392015-12-01 14:24:20 +010041 struct uartlite_platdata *plat = dev_get_platdata(dev);
42 struct uartlite *regs = plat->regs;
Michal Simek49a23e42011-09-25 21:03:08 +000043
Michal Simek93768392015-12-01 14:24:20 +010044 if (in_be32(&regs->status) & SR_TX_FIFO_FULL)
45 return -EAGAIN;
Michal Simek49a23e42011-09-25 21:03:08 +000046
Michal Simek93768392015-12-01 14:24:20 +010047 out_be32(&regs->tx_fifo, ch & 0xff);
48
49 return 0;
Michal Simek49a23e42011-09-25 21:03:08 +000050}
51
Michal Simek93768392015-12-01 14:24:20 +010052static int uartlite_serial_getc(struct udevice *dev)
Michal Simek49a23e42011-09-25 21:03:08 +000053{
Michal Simek93768392015-12-01 14:24:20 +010054 struct uartlite_platdata *plat = dev_get_platdata(dev);
55 struct uartlite *regs = plat->regs;
Michal Simek49a23e42011-09-25 21:03:08 +000056
Michal Simek93768392015-12-01 14:24:20 +010057 if (!(in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA))
58 return -EAGAIN;
Michal Simek49a23e42011-09-25 21:03:08 +000059
Michal Simek49a23e42011-09-25 21:03:08 +000060 return in_be32(&regs->rx_fifo) & 0xff;
61}
62
Michal Simek93768392015-12-01 14:24:20 +010063static int uartlite_serial_pending(struct udevice *dev, bool input)
Michal Simek49a23e42011-09-25 21:03:08 +000064{
Michal Simek93768392015-12-01 14:24:20 +010065 struct uartlite_platdata *plat = dev_get_platdata(dev);
66 struct uartlite *regs = plat->regs;
Michal Simek49a23e42011-09-25 21:03:08 +000067
Michal Simek93768392015-12-01 14:24:20 +010068 if (input)
69 return in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA;
70
71 return !(in_be32(&regs->status) & SR_TX_FIFO_EMPTY);
Michal Simek49a23e42011-09-25 21:03:08 +000072}
73
Michal Simek93768392015-12-01 14:24:20 +010074static int uartlite_serial_probe(struct udevice *dev)
Michal Simek25239e12012-07-02 10:32:18 +020075{
Michal Simek93768392015-12-01 14:24:20 +010076 struct uartlite_platdata *plat = dev_get_platdata(dev);
77 struct uartlite *regs = plat->regs;
Michal Simek8c3bd6b2014-01-21 07:29:47 +010078
Michal Simek93768392015-12-01 14:24:20 +010079 out_be32(&regs->control, 0);
80 out_be32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
81 in_be32(&regs->control);
Michal Simek8c3bd6b2014-01-21 07:29:47 +010082
Michal Simek93768392015-12-01 14:24:20 +010083 return 0;
Michal Simek25239e12012-07-02 10:32:18 +020084}
85
Michal Simek93768392015-12-01 14:24:20 +010086static int uartlite_serial_ofdata_to_platdata(struct udevice *dev)
Michal Simek49a23e42011-09-25 21:03:08 +000087{
Michal Simek93768392015-12-01 14:24:20 +010088 struct uartlite_platdata *plat = dev_get_platdata(dev);
Michal Simek25239e12012-07-02 10:32:18 +020089
Michal Simek93768392015-12-01 14:24:20 +010090 plat->regs = (struct uartlite *)dev_get_addr(dev);
91
92 return 0;
Michal Simek49a23e42011-09-25 21:03:08 +000093}
Marek Vasut87d69222012-09-12 19:45:58 +020094
Michal Simek93768392015-12-01 14:24:20 +010095static const struct dm_serial_ops uartlite_serial_ops = {
96 .putc = uartlite_serial_putc,
97 .pending = uartlite_serial_pending,
98 .getc = uartlite_serial_getc,
99};
100
101static const struct udevice_id uartlite_serial_ids[] = {
102 { .compatible = "xlnx,opb-uartlite-1.00.b", },
103 { .compatible = "xlnx,xps-uartlite-1.00.a" },
104 { }
105};
106
107U_BOOT_DRIVER(serial_uartlite) = {
108 .name = "serial_uartlite",
109 .id = UCLASS_SERIAL,
110 .of_match = uartlite_serial_ids,
111 .ofdata_to_platdata = uartlite_serial_ofdata_to_platdata,
112 .platdata_auto_alloc_size = sizeof(struct uartlite_platdata),
113 .probe = uartlite_serial_probe,
114 .ops = &uartlite_serial_ops,
115 .flags = DM_FLAG_PRE_RELOC,
116};
Michal Simek4166ba32015-12-14 16:55:10 +0100117
118#ifdef CONFIG_DEBUG_UART_UARTLITE
119
120#include <debug_uart.h>
121
122static inline void _debug_uart_init(void)
123{
124 struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
125
126 out_be32(&regs->control, 0);
127 out_be32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
128 in_be32(&regs->control);
129}
130
131static inline void _debug_uart_putc(int ch)
132{
133 struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
134
135 while (in_be32(&regs->status) & SR_TX_FIFO_FULL)
136 ;
137
138 out_be32(&regs->tx_fifo, ch & 0xff);
139}
140
141DEBUG_UART_FUNCS
142#endif