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Jaehoon Chung757bff42012-10-15 19:10:29 +00001/*
2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
4 * Rajeshawari Shinde <rajeshwari.s@samsung.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Jaehoon Chung757bff42012-10-15 19:10:29 +00007 */
8
Alexey Brodkin2a7a2102013-12-26 15:29:07 +04009#include <bouncebuf.h>
Jaehoon Chung757bff42012-10-15 19:10:29 +000010#include <common.h>
Simon Glass1c87ffe2015-08-06 20:16:27 -060011#include <errno.h>
Jaehoon Chung757bff42012-10-15 19:10:29 +000012#include <malloc.h>
Simon Glasscf92e052015-09-02 17:24:58 -060013#include <memalign.h>
Jaehoon Chung757bff42012-10-15 19:10:29 +000014#include <mmc.h>
15#include <dwmmc.h>
Jaehoon Chung757bff42012-10-15 19:10:29 +000016
17#define PAGE_SIZE 4096
18
19static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
20{
21 unsigned long timeout = 1000;
22 u32 ctrl;
23
24 dwmci_writel(host, DWMCI_CTRL, value);
25
26 while (timeout--) {
27 ctrl = dwmci_readl(host, DWMCI_CTRL);
28 if (!(ctrl & DWMCI_RESET_ALL))
29 return 1;
30 }
31 return 0;
32}
33
34static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
35 u32 desc0, u32 desc1, u32 desc2)
36{
37 struct dwmci_idmac *desc = idmac;
38
39 desc->flags = desc0;
40 desc->cnt = desc1;
41 desc->addr = desc2;
Prabhakar Kushwaha41f7be32015-10-25 13:18:25 +053042 desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
Jaehoon Chung757bff42012-10-15 19:10:29 +000043}
44
45static void dwmci_prepare_data(struct dwmci_host *host,
Alexey Brodkin2a7a2102013-12-26 15:29:07 +040046 struct mmc_data *data,
47 struct dwmci_idmac *cur_idmac,
48 void *bounce_buffer)
Jaehoon Chung757bff42012-10-15 19:10:29 +000049{
50 unsigned long ctrl;
51 unsigned int i = 0, flags, cnt, blk_cnt;
Alexey Brodkin2a7a2102013-12-26 15:29:07 +040052 ulong data_start, data_end;
Jaehoon Chung757bff42012-10-15 19:10:29 +000053
54
55 blk_cnt = data->blocks;
56
57 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
58
59 data_start = (ulong)cur_idmac;
Prabhakar Kushwaha41f7be32015-10-25 13:18:25 +053060 dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
Jaehoon Chung757bff42012-10-15 19:10:29 +000061
Jaehoon Chung757bff42012-10-15 19:10:29 +000062 do {
63 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
64 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
65 if (blk_cnt <= 8) {
66 flags |= DWMCI_IDMAC_LD;
67 cnt = data->blocksize * blk_cnt;
68 } else
69 cnt = data->blocksize * 8;
70
71 dwmci_set_idma_desc(cur_idmac, flags, cnt,
Prabhakar Kushwaha41f7be32015-10-25 13:18:25 +053072 (ulong)bounce_buffer + (i * PAGE_SIZE));
Jaehoon Chung757bff42012-10-15 19:10:29 +000073
Mischa Jonker21bd5762013-07-26 16:18:40 +020074 if (blk_cnt <= 8)
Jaehoon Chung757bff42012-10-15 19:10:29 +000075 break;
76 blk_cnt -= 8;
77 cur_idmac++;
78 i++;
79 } while(1);
80
81 data_end = (ulong)cur_idmac;
82 flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
83
84 ctrl = dwmci_readl(host, DWMCI_CTRL);
85 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
86 dwmci_writel(host, DWMCI_CTRL, ctrl);
87
88 ctrl = dwmci_readl(host, DWMCI_BMOD);
89 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
90 dwmci_writel(host, DWMCI_BMOD, ctrl);
91
92 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
93 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
94}
95
huang lina65f51b2015-11-17 14:20:22 +080096static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
huang linf382eb82015-11-17 14:20:21 +080097{
98 int ret = 0;
huang lina65f51b2015-11-17 14:20:22 +080099 u32 timeout = 240000;
100 u32 mask, size, i, len = 0;
101 u32 *buf = NULL;
huang linf382eb82015-11-17 14:20:21 +0800102 ulong start = get_timer(0);
huang lina65f51b2015-11-17 14:20:22 +0800103 u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
104 RX_WMARK_SHIFT) + 1) * 2;
105
106 size = data->blocksize * data->blocks / 4;
107 if (data->flags == MMC_DATA_READ)
108 buf = (unsigned int *)data->dest;
109 else
110 buf = (unsigned int *)data->src;
huang linf382eb82015-11-17 14:20:21 +0800111
112 for (;;) {
113 mask = dwmci_readl(host, DWMCI_RINTSTS);
114 /* Error during data transfer. */
115 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
116 debug("%s: DATA ERROR!\n", __func__);
117 ret = -EINVAL;
118 break;
119 }
120
huang lina65f51b2015-11-17 14:20:22 +0800121 if (host->fifo_mode && size) {
Xu Ziyuan720724d2016-07-28 10:25:48 +0800122 len = 0;
Jacob Chen2b429032016-09-19 10:16:50 +0800123 if (data->flags == MMC_DATA_READ &&
124 (mask & DWMCI_INTMSK_RXDR)) {
125 while (size) {
huang lina65f51b2015-11-17 14:20:22 +0800126 len = dwmci_readl(host, DWMCI_STATUS);
127 len = (len >> DWMCI_FIFO_SHIFT) &
128 DWMCI_FIFO_MASK;
Xu Ziyuan2990e072016-07-28 10:25:47 +0800129 len = min(size, len);
huang lina65f51b2015-11-17 14:20:22 +0800130 for (i = 0; i < len; i++)
131 *buf++ =
132 dwmci_readl(host, DWMCI_DATA);
Jacob Chen2b429032016-09-19 10:16:50 +0800133 size = size > len ? (size - len) : 0;
huang lina65f51b2015-11-17 14:20:22 +0800134 }
Jacob Chen2b429032016-09-19 10:16:50 +0800135 dwmci_writel(host, DWMCI_RINTSTS,
136 DWMCI_INTMSK_RXDR);
137 } else if (data->flags == MMC_DATA_WRITE &&
138 (mask & DWMCI_INTMSK_TXDR)) {
139 while (size) {
huang lina65f51b2015-11-17 14:20:22 +0800140 len = dwmci_readl(host, DWMCI_STATUS);
141 len = fifo_depth - ((len >>
142 DWMCI_FIFO_SHIFT) &
143 DWMCI_FIFO_MASK);
Xu Ziyuan2990e072016-07-28 10:25:47 +0800144 len = min(size, len);
huang lina65f51b2015-11-17 14:20:22 +0800145 for (i = 0; i < len; i++)
146 dwmci_writel(host, DWMCI_DATA,
147 *buf++);
Jacob Chen2b429032016-09-19 10:16:50 +0800148 size = size > len ? (size - len) : 0;
huang lina65f51b2015-11-17 14:20:22 +0800149 }
Jacob Chen2b429032016-09-19 10:16:50 +0800150 dwmci_writel(host, DWMCI_RINTSTS,
151 DWMCI_INTMSK_TXDR);
huang lina65f51b2015-11-17 14:20:22 +0800152 }
huang lina65f51b2015-11-17 14:20:22 +0800153 }
154
huang linf382eb82015-11-17 14:20:21 +0800155 /* Data arrived correctly. */
156 if (mask & DWMCI_INTMSK_DTO) {
157 ret = 0;
158 break;
159 }
160
161 /* Check for timeout. */
162 if (get_timer(start) > timeout) {
163 debug("%s: Timeout waiting for data!\n",
164 __func__);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900165 ret = -ETIMEDOUT;
huang linf382eb82015-11-17 14:20:21 +0800166 break;
167 }
168 }
169
170 dwmci_writel(host, DWMCI_RINTSTS, mask);
171
172 return ret;
173}
174
Jaehoon Chung757bff42012-10-15 19:10:29 +0000175static int dwmci_set_transfer_mode(struct dwmci_host *host,
176 struct mmc_data *data)
177{
178 unsigned long mode;
179
180 mode = DWMCI_CMD_DATA_EXP;
181 if (data->flags & MMC_DATA_WRITE)
182 mode |= DWMCI_CMD_RW;
183
184 return mode;
185}
186
Simon Glass691272f2016-06-12 23:30:23 -0600187#ifdef CONFIG_DM_MMC_OPS
Jaehoon Chung56283472016-06-28 15:52:21 +0900188static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
Simon Glass691272f2016-06-12 23:30:23 -0600189 struct mmc_data *data)
190{
191 struct mmc *mmc = mmc_get_mmc_dev(dev);
192#else
Jaehoon Chung757bff42012-10-15 19:10:29 +0000193static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
194 struct mmc_data *data)
195{
Simon Glass691272f2016-06-12 23:30:23 -0600196#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200197 struct dwmci_host *host = mmc->priv;
Mischa Jonker2136d222013-07-26 14:08:14 +0200198 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
Mischa Jonker21bd5762013-07-26 16:18:40 +0200199 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
Marek Vasut9042d972015-07-27 22:39:38 +0200200 int ret = 0, flags = 0, i;
Xu Ziyuan02ebd422016-07-19 09:38:22 +0800201 unsigned int timeout = 500;
Alexander Graf9b5b8b62016-03-04 01:09:52 +0100202 u32 retry = 100000;
Jaehoon Chung757bff42012-10-15 19:10:29 +0000203 u32 mask, ctrl;
Amar9c50e352013-04-27 11:42:54 +0530204 ulong start = get_timer(0);
Alexey Brodkin2a7a2102013-12-26 15:29:07 +0400205 struct bounce_buffer bbstate;
Jaehoon Chung757bff42012-10-15 19:10:29 +0000206
207 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
Amar9c50e352013-04-27 11:42:54 +0530208 if (get_timer(start) > timeout) {
Simon Glass1c87ffe2015-08-06 20:16:27 -0600209 debug("%s: Timeout on data busy\n", __func__);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900210 return -ETIMEDOUT;
Jaehoon Chung757bff42012-10-15 19:10:29 +0000211 }
Jaehoon Chung757bff42012-10-15 19:10:29 +0000212 }
213
214 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
215
Alexey Brodkin2a7a2102013-12-26 15:29:07 +0400216 if (data) {
huang lina65f51b2015-11-17 14:20:22 +0800217 if (host->fifo_mode) {
218 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
219 dwmci_writel(host, DWMCI_BYTCNT,
220 data->blocksize * data->blocks);
221 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
Alexey Brodkin2a7a2102013-12-26 15:29:07 +0400222 } else {
huang lina65f51b2015-11-17 14:20:22 +0800223 if (data->flags == MMC_DATA_READ) {
224 bounce_buffer_start(&bbstate, (void*)data->dest,
225 data->blocksize *
226 data->blocks, GEN_BB_WRITE);
227 } else {
228 bounce_buffer_start(&bbstate, (void*)data->src,
229 data->blocksize *
230 data->blocks, GEN_BB_READ);
231 }
232 dwmci_prepare_data(host, data, cur_idmac,
233 bbstate.bounce_buffer);
Alexey Brodkin2a7a2102013-12-26 15:29:07 +0400234 }
Alexey Brodkin2a7a2102013-12-26 15:29:07 +0400235 }
Jaehoon Chung757bff42012-10-15 19:10:29 +0000236
Jaehoon Chung757bff42012-10-15 19:10:29 +0000237 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
238
239 if (data)
240 flags = dwmci_set_transfer_mode(host, data);
241
242 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
243 return -1;
244
245 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
246 flags |= DWMCI_CMD_ABORT_STOP;
247 else
248 flags |= DWMCI_CMD_PRV_DAT_WAIT;
249
250 if (cmd->resp_type & MMC_RSP_PRESENT) {
251 flags |= DWMCI_CMD_RESP_EXP;
252 if (cmd->resp_type & MMC_RSP_136)
253 flags |= DWMCI_CMD_RESP_LENGTH;
254 }
255
256 if (cmd->resp_type & MMC_RSP_CRC)
257 flags |= DWMCI_CMD_CHECK_CRC;
258
259 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
260
261 debug("Sending CMD%d\n",cmd->cmdidx);
262
263 dwmci_writel(host, DWMCI_CMD, flags);
264
265 for (i = 0; i < retry; i++) {
266 mask = dwmci_readl(host, DWMCI_RINTSTS);
267 if (mask & DWMCI_INTMSK_CDONE) {
268 if (!data)
269 dwmci_writel(host, DWMCI_RINTSTS, mask);
270 break;
271 }
272 }
273
Pavel Machekf33c9302014-09-05 12:49:48 +0200274 if (i == retry) {
Simon Glass1c87ffe2015-08-06 20:16:27 -0600275 debug("%s: Timeout.\n", __func__);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900276 return -ETIMEDOUT;
Pavel Machekf33c9302014-09-05 12:49:48 +0200277 }
Jaehoon Chung757bff42012-10-15 19:10:29 +0000278
279 if (mask & DWMCI_INTMSK_RTO) {
Pavel Machekf33c9302014-09-05 12:49:48 +0200280 /*
281 * Timeout here is not necessarily fatal. (e)MMC cards
282 * will splat here when they receive CMD55 as they do
283 * not support this command and that is exactly the way
284 * to tell them apart from SD cards. Thus, this output
285 * below shall be debug(). eMMC cards also do not favor
286 * CMD8, please keep that in mind.
287 */
288 debug("%s: Response Timeout.\n", __func__);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900289 return -ETIMEDOUT;
Jaehoon Chung757bff42012-10-15 19:10:29 +0000290 } else if (mask & DWMCI_INTMSK_RE) {
Simon Glass1c87ffe2015-08-06 20:16:27 -0600291 debug("%s: Response Error.\n", __func__);
292 return -EIO;
Jaehoon Chung757bff42012-10-15 19:10:29 +0000293 }
294
295
296 if (cmd->resp_type & MMC_RSP_PRESENT) {
297 if (cmd->resp_type & MMC_RSP_136) {
298 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
299 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
300 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
301 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
302 } else {
303 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
304 }
305 }
306
307 if (data) {
huang lina65f51b2015-11-17 14:20:22 +0800308 ret = dwmci_data_transfer(host, data);
Jaehoon Chung757bff42012-10-15 19:10:29 +0000309
huang lina65f51b2015-11-17 14:20:22 +0800310 /* only dma mode need it */
311 if (!host->fifo_mode) {
312 ctrl = dwmci_readl(host, DWMCI_CTRL);
313 ctrl &= ~(DWMCI_DMA_EN);
314 dwmci_writel(host, DWMCI_CTRL, ctrl);
315 bounce_buffer_stop(&bbstate);
316 }
Jaehoon Chung757bff42012-10-15 19:10:29 +0000317 }
318
319 udelay(100);
320
Marek Vasut9042d972015-07-27 22:39:38 +0200321 return ret;
Jaehoon Chung757bff42012-10-15 19:10:29 +0000322}
323
324static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
325{
326 u32 div, status;
327 int timeout = 10000;
328 unsigned long sclk;
329
Amar9c50e352013-04-27 11:42:54 +0530330 if ((freq == host->clock) || (freq == 0))
Jaehoon Chung757bff42012-10-15 19:10:29 +0000331 return 0;
Jaehoon Chung757bff42012-10-15 19:10:29 +0000332 /*
Pavel Machekf33c9302014-09-05 12:49:48 +0200333 * If host->get_mmc_clk isn't defined,
Jaehoon Chung757bff42012-10-15 19:10:29 +0000334 * then assume that host->bus_hz is source clock value.
Pavel Machekf33c9302014-09-05 12:49:48 +0200335 * host->bus_hz should be set by user.
Jaehoon Chung757bff42012-10-15 19:10:29 +0000336 */
Jaehoon Chungb44fe832013-10-06 18:59:31 +0900337 if (host->get_mmc_clk)
Simon Glasse3563f22015-08-30 16:55:15 -0600338 sclk = host->get_mmc_clk(host, freq);
Jaehoon Chung757bff42012-10-15 19:10:29 +0000339 else if (host->bus_hz)
340 sclk = host->bus_hz;
341 else {
Simon Glass1c87ffe2015-08-06 20:16:27 -0600342 debug("%s: Didn't get source clock value.\n", __func__);
Jaehoon Chung757bff42012-10-15 19:10:29 +0000343 return -EINVAL;
344 }
345
Chin Liang See6ace1532014-06-10 01:26:52 -0500346 if (sclk == freq)
347 div = 0; /* bypass mode */
348 else
349 div = DIV_ROUND_UP(sclk, 2 * freq);
Jaehoon Chung757bff42012-10-15 19:10:29 +0000350
351 dwmci_writel(host, DWMCI_CLKENA, 0);
352 dwmci_writel(host, DWMCI_CLKSRC, 0);
353
354 dwmci_writel(host, DWMCI_CLKDIV, div);
355 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
356 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
357
358 do {
359 status = dwmci_readl(host, DWMCI_CMD);
360 if (timeout-- < 0) {
Simon Glass1c87ffe2015-08-06 20:16:27 -0600361 debug("%s: Timeout!\n", __func__);
Jaehoon Chung757bff42012-10-15 19:10:29 +0000362 return -ETIMEDOUT;
363 }
364 } while (status & DWMCI_CMD_START);
365
366 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
367 DWMCI_CLKEN_LOW_PWR);
368
369 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
370 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
371
372 timeout = 10000;
373 do {
374 status = dwmci_readl(host, DWMCI_CMD);
375 if (timeout-- < 0) {
Simon Glass1c87ffe2015-08-06 20:16:27 -0600376 debug("%s: Timeout!\n", __func__);
Jaehoon Chung757bff42012-10-15 19:10:29 +0000377 return -ETIMEDOUT;
378 }
379 } while (status & DWMCI_CMD_START);
380
381 host->clock = freq;
382
383 return 0;
384}
385
Simon Glass691272f2016-06-12 23:30:23 -0600386#ifdef CONFIG_DM_MMC_OPS
Jaehoon Chung56283472016-06-28 15:52:21 +0900387static int dwmci_set_ios(struct udevice *dev)
Simon Glass691272f2016-06-12 23:30:23 -0600388{
389 struct mmc *mmc = mmc_get_mmc_dev(dev);
390#else
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900391static int dwmci_set_ios(struct mmc *mmc)
Jaehoon Chung757bff42012-10-15 19:10:29 +0000392{
Simon Glass691272f2016-06-12 23:30:23 -0600393#endif
Jaehoon Chung045bdcd2014-05-16 13:59:55 +0900394 struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
395 u32 ctype, regs;
Jaehoon Chung757bff42012-10-15 19:10:29 +0000396
Pavel Machekf33c9302014-09-05 12:49:48 +0200397 debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
Jaehoon Chung757bff42012-10-15 19:10:29 +0000398
399 dwmci_setup_bus(host, mmc->clock);
400 switch (mmc->bus_width) {
401 case 8:
402 ctype = DWMCI_CTYPE_8BIT;
403 break;
404 case 4:
405 ctype = DWMCI_CTYPE_4BIT;
406 break;
407 default:
408 ctype = DWMCI_CTYPE_1BIT;
409 break;
410 }
411
412 dwmci_writel(host, DWMCI_CTYPE, ctype);
413
Jaehoon Chung045bdcd2014-05-16 13:59:55 +0900414 regs = dwmci_readl(host, DWMCI_UHS_REG);
Andrew Gabbasov2b8a9692014-12-01 06:59:12 -0600415 if (mmc->ddr_mode)
Jaehoon Chung045bdcd2014-05-16 13:59:55 +0900416 regs |= DWMCI_DDR_MODE;
417 else
Jaehoon Chungafc9e2b2015-01-14 17:37:53 +0900418 regs &= ~DWMCI_DDR_MODE;
Jaehoon Chung045bdcd2014-05-16 13:59:55 +0900419
420 dwmci_writel(host, DWMCI_UHS_REG, regs);
421
Jaehoon Chung757bff42012-10-15 19:10:29 +0000422 if (host->clksel)
423 host->clksel(host);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900424
Simon Glass691272f2016-06-12 23:30:23 -0600425 return 0;
Jaehoon Chung757bff42012-10-15 19:10:29 +0000426}
427
428static int dwmci_init(struct mmc *mmc)
429{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200430 struct dwmci_host *host = mmc->priv;
Jaehoon Chung757bff42012-10-15 19:10:29 +0000431
Jaehoon Chung18ab6752013-11-29 20:08:57 +0900432 if (host->board_init)
433 host->board_init(host);
Rajeshwari Shinde6f0b7ca2013-10-29 12:53:13 +0530434
Jaehoon Chung757bff42012-10-15 19:10:29 +0000435 dwmci_writel(host, DWMCI_PWREN, 1);
436
437 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
Simon Glass1c87ffe2015-08-06 20:16:27 -0600438 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
439 return -EIO;
Jaehoon Chung757bff42012-10-15 19:10:29 +0000440 }
441
Amar9c50e352013-04-27 11:42:54 +0530442 /* Enumerate at 400KHz */
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200443 dwmci_setup_bus(host, mmc->cfg->f_min);
Amar9c50e352013-04-27 11:42:54 +0530444
Jaehoon Chung757bff42012-10-15 19:10:29 +0000445 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
446 dwmci_writel(host, DWMCI_INTMASK, 0);
447
448 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
449
450 dwmci_writel(host, DWMCI_IDINTEN, 0);
451 dwmci_writel(host, DWMCI_BMOD, 1);
452
Simon Glass760177d2015-08-06 20:16:29 -0600453 if (!host->fifoth_val) {
454 uint32_t fifo_size;
455
456 fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
457 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
458 host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
459 TX_WMARK(fifo_size / 2);
Amar9c50e352013-04-27 11:42:54 +0530460 }
Simon Glass760177d2015-08-06 20:16:29 -0600461 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
Jaehoon Chung757bff42012-10-15 19:10:29 +0000462
463 dwmci_writel(host, DWMCI_CLKENA, 0);
464 dwmci_writel(host, DWMCI_CLKSRC, 0);
465
466 return 0;
467}
468
Simon Glass691272f2016-06-12 23:30:23 -0600469#ifdef CONFIG_DM_MMC_OPS
470int dwmci_probe(struct udevice *dev)
471{
472 struct mmc *mmc = mmc_get_mmc_dev(dev);
473
474 return dwmci_init(mmc);
475}
476
477const struct dm_mmc_ops dm_dwmci_ops = {
478 .send_cmd = dwmci_send_cmd,
479 .set_ios = dwmci_set_ios,
480};
481
482#else
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200483static const struct mmc_ops dwmci_ops = {
484 .send_cmd = dwmci_send_cmd,
485 .set_ios = dwmci_set_ios,
486 .init = dwmci_init,
487};
Simon Glass691272f2016-06-12 23:30:23 -0600488#endif
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200489
Jaehoon Chunge5113c32016-09-23 19:13:16 +0900490void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
491 u32 max_clk, u32 min_clk)
Simon Glass5e6ff812016-05-14 14:03:07 -0600492{
Jaehoon Chunge5113c32016-09-23 19:13:16 +0900493 cfg->name = host->name;
Simon Glass691272f2016-06-12 23:30:23 -0600494#ifndef CONFIG_DM_MMC_OPS
Simon Glass5e6ff812016-05-14 14:03:07 -0600495 cfg->ops = &dwmci_ops;
Simon Glass691272f2016-06-12 23:30:23 -0600496#endif
Simon Glass5e6ff812016-05-14 14:03:07 -0600497 cfg->f_min = min_clk;
498 cfg->f_max = max_clk;
499
500 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
501
Jaehoon Chunge5113c32016-09-23 19:13:16 +0900502 cfg->host_caps = host->caps;
Simon Glass5e6ff812016-05-14 14:03:07 -0600503
Jaehoon Chunge5113c32016-09-23 19:13:16 +0900504 if (host->buswidth == 8) {
Simon Glass5e6ff812016-05-14 14:03:07 -0600505 cfg->host_caps |= MMC_MODE_8BIT;
506 cfg->host_caps &= ~MMC_MODE_4BIT;
507 } else {
508 cfg->host_caps |= MMC_MODE_4BIT;
509 cfg->host_caps &= ~MMC_MODE_8BIT;
510 }
511 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
512
513 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
514}
515
516#ifdef CONFIG_BLK
517int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
518{
519 return mmc_bind(dev, mmc, cfg);
520}
521#else
Jaehoon Chung757bff42012-10-15 19:10:29 +0000522int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
523{
Jaehoon Chunge5113c32016-09-23 19:13:16 +0900524 dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
Jaehoon Chung757bff42012-10-15 19:10:29 +0000525
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200526 host->mmc = mmc_create(&host->cfg, host);
527 if (host->mmc == NULL)
528 return -1;
529
530 return 0;
Jaehoon Chung757bff42012-10-15 19:10:29 +0000531}
Simon Glass5e6ff812016-05-14 14:03:07 -0600532#endif