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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Álvaro Fernández Rojas07661e72017-05-16 18:46:58 +02002/*
3 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
Álvaro Fernández Rojas07661e72017-05-16 18:46:58 +02004 */
5
6#include <dt-bindings/clock/bcm6338-clock.h>
Álvaro Fernández Rojas9ab403d2018-12-01 19:00:16 +01007#include <dt-bindings/dma/bcm6338-dma.h>
Álvaro Fernández Rojas07661e72017-05-16 18:46:58 +02008#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/reset/bcm6338-reset.h>
10#include "skeleton.dtsi"
11
12/ {
13 compatible = "brcm,bcm6338";
14
Álvaro Fernández Rojas0adfb192018-01-23 17:14:59 +010015 aliases {
16 spi0 = &spi;
17 };
18
Álvaro Fernández Rojas07661e72017-05-16 18:46:58 +020019 cpus {
20 reg = <0xfffe0000 0x4>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23 u-boot,dm-pre-reloc;
24
25 cpu@0 {
26 compatible = "brcm,bcm6338-cpu", "mips,mips4Kc";
27 device_type = "cpu";
28 reg = <0>;
29 u-boot,dm-pre-reloc;
30 };
31 };
32
33 clocks {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
37 u-boot,dm-pre-reloc;
38
39 periph_osc: periph-osc {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <50000000>;
43 u-boot,dm-pre-reloc;
44 };
45
46 periph_clk: periph-clk {
47 compatible = "brcm,bcm6345-clk";
48 reg = <0xfffe0004 0x4>;
49 #clock-cells = <1>;
50 };
51 };
52
53 pflash: nor@1fc00000 {
54 compatible = "cfi-flash";
55 reg = <0x1fc00000 0x400000>;
56 bank-width = <2>;
57 #address-cells = <1>;
58 #size-cells = <1>;
59
60 status = "disabled";
61 };
62
63 ubus {
64 compatible = "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <1>;
67 u-boot,dm-pre-reloc;
68
69 pll_cntl: syscon@fffe0008 {
70 compatible = "syscon";
71 reg = <0xfffe0008 0x4>;
72 };
73
74 syscon-reboot {
75 compatible = "syscon-reboot";
76 regmap = <&pll_cntl>;
77 offset = <0x0>;
78 mask = <0x1>;
79 };
80
81 periph_rst: reset-controller@fffe0028 {
82 compatible = "brcm,bcm6345-reset";
83 reg = <0xfffe0028 0x4>;
84 #reset-cells = <1>;
85 };
86
87 wdt: watchdog@fffe021c {
88 compatible = "brcm,bcm6345-wdt";
89 reg = <0xfffe021c 0xc>;
90 clocks = <&periph_osc>;
91 };
92
93 wdt-reboot {
94 compatible = "wdt-reboot";
95 wdt = <&wdt>;
96 };
97
98 uart0: serial@fffe0300 {
99 compatible = "brcm,bcm6345-uart";
100 reg = <0xfffe0300 0x18>;
101 clocks = <&periph_osc>;
102
103 status = "disabled";
104 };
105
106 gpio: gpio-controller@fffe0404 {
107 compatible = "brcm,bcm6345-gpio";
108 reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
109 gpio-controller;
110 #gpio-cells = <2>;
111 ngpios = <8>;
112
113 status = "disabled";
114 };
115
Álvaro Fernández Rojas0adfb192018-01-23 17:14:59 +0100116 spi: spi@fffe0c00 {
117 compatible = "brcm,bcm6348-spi";
118 reg = <0xfffe0c00 0xc0>;
119 #address-cells = <1>;
120 #size-cells = <0>;
121 clocks = <&periph_clk BCM6338_CLK_SPI>;
122 resets = <&periph_rst BCM6338_RST_SPI>;
123 spi-max-frequency = <20000000>;
124 num-cs = <4>;
125
126 status = "disabled";
127 };
128
Álvaro Fernández Rojas07661e72017-05-16 18:46:58 +0200129 memory-controller@fffe3100 {
130 compatible = "brcm,bcm6338-mc";
131 reg = <0xfffe3100 0x38>;
132 u-boot,dm-pre-reloc;
133 };
Álvaro Fernández Rojas9ab403d2018-12-01 19:00:16 +0100134
135 iudma: dma-controller@fffe2400 {
136 compatible = "brcm,bcm6348-iudma";
137 reg = <0xfffe2400 0x1c>,
138 <0xfffe2500 0x60>,
139 <0xfffe2600 0x60>;
140 reg-names = "dma",
141 "dma-channels",
142 "dma-sram";
143 #dma-cells = <1>;
144 dma-channels = <6>;
145 resets = <&periph_rst BCM6338_RST_DMAMEM>;
146 };
Álvaro Fernández Rojasd7f5bc12018-12-01 19:00:25 +0100147
148 enet: ethernet@fffe2800 {
149 compatible = "brcm,bcm6348-enet";
150 #address-cells = <1>;
151 #size-cells = <0>;
152 reg = <0xfffe2800 0x2dc>;
153 clocks = <&periph_clk BCM6338_CLK_ENET>;
154 resets = <&periph_rst BCM6338_RST_ENET>;
155 dmas = <&iudma BCM6338_DMA_ENET_RX>,
156 <&iudma BCM6338_DMA_ENET_TX>;
157 dma-names = "rx",
158 "tx";
159
160 status = "disabled";
161 };
Álvaro Fernández Rojas07661e72017-05-16 18:46:58 +0200162 };
163};