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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefano Babic876a25d2016-06-08 10:50:20 +02002/*
3 * Copyright (C) Stefano Babic <sbabic@denx.de>
Stefano Babic876a25d2016-06-08 10:50:20 +02004 */
5
6
7#ifndef __PCM058_CONFIG_H
8#define __PCM058_CONFIG_H
9
Stefano Babic876a25d2016-06-08 10:50:20 +020010#ifdef CONFIG_SPL
Stefano Babic876a25d2016-06-08 10:50:20 +020011#include "imx6_spl.h"
12#endif
13
14#include "mx6_common.h"
15
16/* Thermal */
17#define CONFIG_IMX_THERMAL
18
19/* Serial */
20#define CONFIG_MXC_UART
21#define CONFIG_MXC_UART_BASE UART2_BASE
Simon Glass12ca05a2016-10-17 20:12:39 -060022#define CONSOLE_DEV "ttymxc1"
Stefano Babic876a25d2016-06-08 10:50:20 +020023
24#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
25
26/* Early setup */
Stefano Babic876a25d2016-06-08 10:50:20 +020027
28
29/* Size of malloc() pool */
30#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
31
32/* Ethernet */
33#define CONFIG_FEC_MXC
Stefano Babic876a25d2016-06-08 10:50:20 +020034#define IMX_FEC_BASE ENET_BASE_ADDR
35#define CONFIG_FEC_XCV_TYPE RGMII
36#define CONFIG_ETHPRIME "FEC"
37#define CONFIG_FEC_MXC_PHYADDR 3
38
Stefano Babic876a25d2016-06-08 10:50:20 +020039/* SPI Flash */
Stefano Babic876a25d2016-06-08 10:50:20 +020040
41/* I2C Configs */
42#define CONFIG_SYS_I2C
43#define CONFIG_SYS_I2C_MXC
44#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 2 */
45#define CONFIG_SYS_I2C_SPEED 100000
46
47#ifndef CONFIG_SPL_BUILD
Stefano Babic876a25d2016-06-08 10:50:20 +020048/* Enable NAND support */
Stefano Babic876a25d2016-06-08 10:50:20 +020049#define CONFIG_SYS_MAX_NAND_DEVICE 1
50#define CONFIG_SYS_NAND_BASE 0x40000000
51#define CONFIG_SYS_NAND_5_ADDR_CYCLE
52#define CONFIG_SYS_NAND_ONFI_DETECTION
53#endif
54
55/* DMA stuff, needed for GPMI/MXS NAND support */
Stefano Babic876a25d2016-06-08 10:50:20 +020056
57/* Filesystem support */
Stefano Babic876a25d2016-06-08 10:50:20 +020058
Stefano Babic876a25d2016-06-08 10:50:20 +020059/* Physical Memory Map */
Stefano Babic876a25d2016-06-08 10:50:20 +020060#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
61
62#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
63#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
64#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
65
66#define CONFIG_SYS_INIT_SP_OFFSET \
67 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
68#define CONFIG_SYS_INIT_SP_ADDR \
69 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
70
71/* MMC Configs */
72#define CONFIG_SYS_FSL_ESDHC_ADDR 0
73#define CONFIG_SYS_FSL_USDHC_NUM 1
74
75/* Environment organization */
Stefano Babic876a25d2016-06-08 10:50:20 +020076#define CONFIG_ENV_SIZE (16 * 1024)
77#define CONFIG_ENV_OFFSET (1024 * SZ_1K)
78#define CONFIG_ENV_SECT_SIZE (64 * SZ_1K)
Stefano Babic876a25d2016-06-08 10:50:20 +020079#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
80 CONFIG_ENV_SECT_SIZE)
Stefano Babic876a25d2016-06-08 10:50:20 +020081
82#ifdef CONFIG_ENV_IS_IN_NAND
83#define CONFIG_ENV_OFFSET (0x1E0000)
84#define CONFIG_ENV_SECT_SIZE (128 * SZ_1K)
85#endif
86
87#endif