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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
David Brownell7a4f5112009-05-15 23:47:12 +02002/*
3 * Copyright (C) 2004 Texas Instruments.
4 * Copyright (C) 2009 David Brownell
David Brownell7a4f5112009-05-15 23:47:12 +02005 */
6
7#include <common.h>
8#include <asm/arch/hardware.h>
Sekhar Nori91172ba2009-11-12 11:07:22 -05009#include <asm/io.h>
David Brownell7a4f5112009-05-15 23:47:12 +020010
Hadli, Manjunath8f5d4682012-02-06 00:30:44 +000011DECLARE_GLOBAL_DATA_PTR;
12
David Brownell7a4f5112009-05-15 23:47:12 +020013/* offsets from PLL controller base */
14#define PLLC_PLLCTL 0x100
15#define PLLC_PLLM 0x110
16#define PLLC_PREDIV 0x114
17#define PLLC_PLLDIV1 0x118
18#define PLLC_PLLDIV2 0x11c
19#define PLLC_PLLDIV3 0x120
20#define PLLC_POSTDIV 0x128
21#define PLLC_BPDIV 0x12c
22#define PLLC_PLLDIV4 0x160
23#define PLLC_PLLDIV5 0x164
24#define PLLC_PLLDIV6 0x168
Sudhakar Rajashekharab7e68432011-09-03 22:18:04 -040025#define PLLC_PLLDIV7 0x16c
David Brownell7a4f5112009-05-15 23:47:12 +020026#define PLLC_PLLDIV8 0x170
27#define PLLC_PLLDIV9 0x174
28
Sudhakar Rajashekharab7e68432011-09-03 22:18:04 -040029unsigned int sysdiv[9] = {
30 PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
31 PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
Sekhar Nori91172ba2009-11-12 11:07:22 -050032};
33
34int clk_get(enum davinci_clk_ids id)
35{
36 int pre_div;
37 int pllm;
38 int post_div;
39 int pll_out;
Sudhakar Rajashekharab7e68432011-09-03 22:18:04 -040040 unsigned int pll_base;
Sekhar Nori91172ba2009-11-12 11:07:22 -050041
42 pll_out = CONFIG_SYS_OSCIN_FREQ;
43
44 if (id == DAVINCI_AUXCLK_CLKID)
45 goto out;
46
Sudhakar Rajashekharab7e68432011-09-03 22:18:04 -040047 if ((id >> 16) == 1)
48 pll_base = (unsigned int)davinci_pllc1_regs;
49 else
50 pll_base = (unsigned int)davinci_pllc0_regs;
51
52 id &= 0xFFFF;
53
Sekhar Nori91172ba2009-11-12 11:07:22 -050054 /*
55 * Lets keep this simple. Combining operations can result in
56 * unexpected approximations
57 */
Sudhakar Rajashekharab7e68432011-09-03 22:18:04 -040058 pre_div = (readl(pll_base + PLLC_PREDIV) &
59 DAVINCI_PLLC_DIV_MASK) + 1;
60 pllm = readl(pll_base + PLLC_PLLM) + 1;
Sekhar Nori91172ba2009-11-12 11:07:22 -050061
62 pll_out /= pre_div;
63 pll_out *= pllm;
64
65 if (id == DAVINCI_PLLM_CLKID)
66 goto out;
67
Sudhakar Rajashekharab7e68432011-09-03 22:18:04 -040068 post_div = (readl(pll_base + PLLC_POSTDIV) &
69 DAVINCI_PLLC_DIV_MASK) + 1;
Sekhar Nori91172ba2009-11-12 11:07:22 -050070
71 pll_out /= post_div;
72
73 if (id == DAVINCI_PLLC_CLKID)
74 goto out;
75
Sudhakar Rajashekharab7e68432011-09-03 22:18:04 -040076 pll_out /= (readl(pll_base + sysdiv[id - 1]) &
77 DAVINCI_PLLC_DIV_MASK) + 1;
Sekhar Nori91172ba2009-11-12 11:07:22 -050078
79out:
80 return pll_out;
81}
Laurence Withersbe7d2572012-07-30 23:30:37 +000082
83int set_cpu_clk_info(void)
84{
85 gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
86 /* DDR PHY uses an x2 input clock */
87 gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
88 (clk_get(DAVINCI_DDR_CLKID) / 1000000);
89 gd->bd->bi_dsp_freq = 0;
90 return 0;
91}