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stroese13fdf8a2003-09-12 08:55:18 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405EP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_PLU405 1 /* ...on a PLU405 board */
stroese13fdf8a2003-09-12 08:55:18 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroese13fdf8a2003-09-12 08:55:18 +000042
stroesea20b27a2004-12-16 18:05:42 +000043#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
stroese13fdf8a2003-09-12 08:55:18 +000044
45#define CONFIG_BAUDRATE 9600
stroese13fdf8a2003-09-12 08:55:18 +000046
47#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000048#undef CONFIG_BOOTCOMMAND
stroese13fdf8a2003-09-12 08:55:18 +000049
stroesea20b27a2004-12-16 18:05:42 +000050#define CONFIG_PREBOOT /* enable preboot variable */
51
stroese13fdf8a2003-09-12 08:55:18 +000052#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
53
stroesea20b27a2004-12-16 18:05:42 +000054#if 0 /* test-only */
55#define CONFIG_NET_MULTI 1
56
stroese13fdf8a2003-09-12 08:55:18 +000057#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000058#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000059#define CONFIG_PHY1_ADDR 1 /* PHY address */
60#else
61#define CONFIG_MII 1 /* MII PHY management */
62#define CONFIG_PHY_ADDR 0 /* PHY address */
63#endif
64#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
65
66#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
stroese13fdf8a2003-09-12 08:55:18 +000067
68#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
69 CFG_CMD_DHCP | \
70 CFG_CMD_PCI | \
71 CFG_CMD_IRQ | \
72 CFG_CMD_IDE | \
stroesea20b27a2004-12-16 18:05:42 +000073 CFG_CMD_FAT | \
stroese13fdf8a2003-09-12 08:55:18 +000074 CFG_CMD_ELF | \
75 CFG_CMD_NAND | \
76 CFG_CMD_DATE | \
77 CFG_CMD_I2C | \
78 CFG_CMD_MII | \
79 CFG_CMD_PING | \
wdenkc837dcb2004-01-20 23:12:12 +000080 CFG_CMD_EEPROM )
stroese13fdf8a2003-09-12 08:55:18 +000081
82#define CONFIG_MAC_PARTITION
83#define CONFIG_DOS_PARTITION
84
stroesea20b27a2004-12-16 18:05:42 +000085#define CONFIG_SUPPORT_VFAT
86
87#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
88#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */
89
stroese13fdf8a2003-09-12 08:55:18 +000090/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
91#include <cmd_confdefs.h>
92
wdenkc837dcb2004-01-20 23:12:12 +000093#undef CONFIG_WATCHDOG /* watchdog disabled */
stroese13fdf8a2003-09-12 08:55:18 +000094
wdenkc837dcb2004-01-20 23:12:12 +000095#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
96#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
stroese13fdf8a2003-09-12 08:55:18 +000097
wdenkc837dcb2004-01-20 23:12:12 +000098#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
stroese13fdf8a2003-09-12 08:55:18 +000099
100/*
101 * Miscellaneous configurable options
102 */
103#define CFG_LONGHELP /* undef to save memory */
104#define CFG_PROMPT "=> " /* Monitor Command Prompt */
105
106#undef CFG_HUSH_PARSER /* use "hush" command parser */
107#ifdef CFG_HUSH_PARSER
wdenkc837dcb2004-01-20 23:12:12 +0000108#define CFG_PROMPT_HUSH_PS2 "> "
stroese13fdf8a2003-09-12 08:55:18 +0000109#endif
110
111#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +0000112#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +0000113#else
wdenkc837dcb2004-01-20 23:12:12 +0000114#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +0000115#endif
116#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
117#define CFG_MAXARGS 16 /* max number of command args */
118#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
119
wdenkc837dcb2004-01-20 23:12:12 +0000120#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
stroese13fdf8a2003-09-12 08:55:18 +0000121
wdenkc837dcb2004-01-20 23:12:12 +0000122#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroese13fdf8a2003-09-12 08:55:18 +0000123
stroesea20b27a2004-12-16 18:05:42 +0000124#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
125
stroese13fdf8a2003-09-12 08:55:18 +0000126#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
127#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
128
wdenkc837dcb2004-01-20 23:12:12 +0000129#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
130#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
131#define CFG_BASE_BAUD 691200
132#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
stroese13fdf8a2003-09-12 08:55:18 +0000133
134/* The following table includes the supported baudrates */
wdenkc837dcb2004-01-20 23:12:12 +0000135#define CFG_BAUDRATE_TABLE \
stroese13fdf8a2003-09-12 08:55:18 +0000136 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
137 57600, 115200, 230400, 460800, 921600 }
138
139#define CFG_LOAD_ADDR 0x100000 /* default load address */
140#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
141
wdenkc837dcb2004-01-20 23:12:12 +0000142#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
stroese13fdf8a2003-09-12 08:55:18 +0000143
144#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
stroesea20b27a2004-12-16 18:05:42 +0000145#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
146
147/* Only interrupt boot if space is pressed */
148/* If a long serial cable is connected but */
149/* other end is dead, garbage will be read */
150#define CONFIG_AUTOBOOT_KEYED 1
151#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
152#undef CONFIG_AUTOBOOT_DELAY_STR
153#define CONFIG_AUTOBOOT_STOP_STR " "
stroese13fdf8a2003-09-12 08:55:18 +0000154
wdenkc837dcb2004-01-20 23:12:12 +0000155#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese13fdf8a2003-09-12 08:55:18 +0000156
wdenkc837dcb2004-01-20 23:12:12 +0000157#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese13fdf8a2003-09-12 08:55:18 +0000158
159/*-----------------------------------------------------------------------
160 * NAND-FLASH stuff
161 *-----------------------------------------------------------------------
162 */
163#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
164#define SECTORSIZE 512
165
166#define ADDR_COLUMN 1
167#define ADDR_PAGE 2
168#define ADDR_COLUMN_PAGE 3
169
wdenkc837dcb2004-01-20 23:12:12 +0000170#define NAND_ChipID_UNKNOWN 0x00
stroese13fdf8a2003-09-12 08:55:18 +0000171#define NAND_MAX_FLOORS 1
172#define NAND_MAX_CHIPS 1
173
wdenkc837dcb2004-01-20 23:12:12 +0000174#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
175#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
176#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
177#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
stroese13fdf8a2003-09-12 08:55:18 +0000178
179#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
180#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
181#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
182#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
183#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
184#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
185#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
186
187#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
188#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
189#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
190#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
191
stroesea20b27a2004-12-16 18:05:42 +0000192#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
193
stroese13fdf8a2003-09-12 08:55:18 +0000194/*-----------------------------------------------------------------------
195 * PCI stuff
196 *-----------------------------------------------------------------------
197 */
stroesea20b27a2004-12-16 18:05:42 +0000198#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
199#define PCI_HOST_FORCE 1 /* configure as pci host */
200#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroese13fdf8a2003-09-12 08:55:18 +0000201
stroesea20b27a2004-12-16 18:05:42 +0000202#define CONFIG_PCI /* include pci support */
203#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
204#define CONFIG_PCI_PNP /* do pci plug-and-play */
205 /* resource configuration */
stroese13fdf8a2003-09-12 08:55:18 +0000206
stroesea20b27a2004-12-16 18:05:42 +0000207#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroese13fdf8a2003-09-12 08:55:18 +0000208
stroesea20b27a2004-12-16 18:05:42 +0000209#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
210
211#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
212#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
213#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
214#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
stroese81b83c92005-05-03 06:12:20 +0000215#define CFG_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */
stroesea20b27a2004-12-16 18:05:42 +0000216#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
217#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
218#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
219#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
stroese13fdf8a2003-09-12 08:55:18 +0000220
221/*-----------------------------------------------------------------------
222 * IDE/ATA stuff
223 *-----------------------------------------------------------------------
224 */
wdenkc837dcb2004-01-20 23:12:12 +0000225#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
226#undef CONFIG_IDE_LED /* no led for ide supported */
stroese13fdf8a2003-09-12 08:55:18 +0000227#define CONFIG_IDE_RESET 1 /* reset for ide supported */
228
wdenkc837dcb2004-01-20 23:12:12 +0000229#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
230#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
stroese13fdf8a2003-09-12 08:55:18 +0000231
wdenkc837dcb2004-01-20 23:12:12 +0000232#define CFG_ATA_BASE_ADDR 0xF0100000
233#define CFG_ATA_IDE0_OFFSET 0x0000
stroese13fdf8a2003-09-12 08:55:18 +0000234
235#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
wdenkc837dcb2004-01-20 23:12:12 +0000236#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
stroese13fdf8a2003-09-12 08:55:18 +0000237#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
238
239/*
240 * For booting Linux, the board info and command line data
241 * have to be in the first 8 MB of memory, since this is
242 * the maximum mapped by the Linux kernel during initialization.
243 */
244#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
245/*-----------------------------------------------------------------------
246 * FLASH organization
247 */
248#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
249
250#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
251#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
252
253#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
254#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
255
wdenkc837dcb2004-01-20 23:12:12 +0000256#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
257#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
258#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroese13fdf8a2003-09-12 08:55:18 +0000259/*
260 * The following defines are added for buggy IOP480 byte interface.
261 * All other boards should use the standard values (CPCI405 etc.)
262 */
wdenkc837dcb2004-01-20 23:12:12 +0000263#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
264#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
265#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
stroese13fdf8a2003-09-12 08:55:18 +0000266
wdenkc837dcb2004-01-20 23:12:12 +0000267#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroese13fdf8a2003-09-12 08:55:18 +0000268
269#if 0 /* test-only */
wdenkc837dcb2004-01-20 23:12:12 +0000270#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
271#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
stroese13fdf8a2003-09-12 08:55:18 +0000272#endif
273
274/*-----------------------------------------------------------------------
275 * Start addresses for the final memory configuration
276 * (Set up by the startup code)
277 * Please note that CFG_SDRAM_BASE _must_ start at 0
278 */
279#define CFG_SDRAM_BASE 0x00000000
280#define CFG_FLASH_BASE 0xFFFC0000
281#define CFG_MONITOR_BASE TEXT_BASE
282#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
283#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
284
285#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
286# define CFG_RAMBOOT 1
287#else
288# undef CFG_RAMBOOT
289#endif
290
291/*-----------------------------------------------------------------------
292 * Environment Variable setup
293 */
wdenkc837dcb2004-01-20 23:12:12 +0000294#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
295#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
296#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
stroese13fdf8a2003-09-12 08:55:18 +0000297 /* total size of a CAT24WC16 is 2048 bytes */
298
299#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
wdenkc837dcb2004-01-20 23:12:12 +0000300#define CFG_NVRAM_SIZE 242 /* NVRAM size */
stroese13fdf8a2003-09-12 08:55:18 +0000301
302/*-----------------------------------------------------------------------
303 * I2C EEPROM (CAT24WC16) for environment
304 */
305#define CONFIG_HARD_I2C /* I2c with hardware support */
306#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
307#define CFG_I2C_SLAVE 0x7F
308
309#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
310#if 1 /* test-only */
311/* CAT24WC08/16... */
wdenkc837dcb2004-01-20 23:12:12 +0000312#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
313/* mask of address bits that overflow into the "EEPROM chip address" */
stroese13fdf8a2003-09-12 08:55:18 +0000314#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
315#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
316 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000317 /* last 4 bits of the address */
stroese13fdf8a2003-09-12 08:55:18 +0000318#else
319/* CAT24WC32/64... */
wdenkc837dcb2004-01-20 23:12:12 +0000320#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
321/* mask of address bits that overflow into the "EEPROM chip address" */
stroese13fdf8a2003-09-12 08:55:18 +0000322#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
323#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
324 /* 32 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000325 /* last 5 bits of the address */
stroese13fdf8a2003-09-12 08:55:18 +0000326#endif
327#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
328#define CFG_EEPROM_PAGE_WRITE_ENABLE
329
330/*-----------------------------------------------------------------------
331 * Cache Configuration
332 */
wdenkc837dcb2004-01-20 23:12:12 +0000333#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
334 /* have only 8kB, 16kB is save here */
stroese13fdf8a2003-09-12 08:55:18 +0000335#define CFG_CACHELINE_SIZE 32 /* ... */
336#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
337#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
338#endif
339
340/*-----------------------------------------------------------------------
341 * External Bus Controller (EBC) Setup
342 */
343
wdenkc837dcb2004-01-20 23:12:12 +0000344#define CAN_BA 0xF0000000 /* CAN Base Address */
345#define DUART0_BA 0xF0000400 /* DUART Base Address */
346#define DUART1_BA 0xF0000408 /* DUART Base Address */
347#define RTC_BA 0xF0000500 /* RTC Base Address */
348#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
349#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000350
wdenkc837dcb2004-01-20 23:12:12 +0000351/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
352#define CFG_EBC_PB0AP 0x92015480
353/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
354#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroese13fdf8a2003-09-12 08:55:18 +0000355
wdenkc837dcb2004-01-20 23:12:12 +0000356/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
357#define CFG_EBC_PB1AP 0x92015480
358#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000359
wdenkc837dcb2004-01-20 23:12:12 +0000360/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
361#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
362#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000363
wdenkc837dcb2004-01-20 23:12:12 +0000364/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
365#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
366#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
stroese13fdf8a2003-09-12 08:55:18 +0000367
368/*-----------------------------------------------------------------------
369 * FPGA stuff
370 */
371
wdenkc837dcb2004-01-20 23:12:12 +0000372#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000373
374/* FPGA internal regs */
wdenkc837dcb2004-01-20 23:12:12 +0000375#define CFG_FPGA_CTRL 0x000
stroese13fdf8a2003-09-12 08:55:18 +0000376
377/* FPGA Control Reg */
wdenkc837dcb2004-01-20 23:12:12 +0000378#define CFG_FPGA_CTRL_CF_RESET 0x0001
379#define CFG_FPGA_CTRL_WDI 0x0002
stroese13fdf8a2003-09-12 08:55:18 +0000380#define CFG_FPGA_CTRL_PS2_RESET 0x0020
381
wdenkc837dcb2004-01-20 23:12:12 +0000382#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
383#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
stroese13fdf8a2003-09-12 08:55:18 +0000384
385/* FPGA program pin configuration */
wdenkc837dcb2004-01-20 23:12:12 +0000386#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
387#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
388#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
389#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
390#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroese13fdf8a2003-09-12 08:55:18 +0000391
392/*-----------------------------------------------------------------------
393 * Definitions for initial stack pointer and data area (in data cache)
394 */
395/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
wdenkc837dcb2004-01-20 23:12:12 +0000396#define CFG_TEMP_STACK_OCM 1
stroese13fdf8a2003-09-12 08:55:18 +0000397
398/* On Chip Memory location */
399#define CFG_OCM_DATA_ADDR 0xF8000000
400#define CFG_OCM_DATA_SIZE 0x1000
401#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
402#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
403
404#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
405#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc837dcb2004-01-20 23:12:12 +0000406#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
stroese13fdf8a2003-09-12 08:55:18 +0000407
408/*-----------------------------------------------------------------------
409 * Definitions for GPIO setup (PPC405EP specific)
410 *
wdenkc837dcb2004-01-20 23:12:12 +0000411 * GPIO0[0] - External Bus Controller BLAST output
412 * GPIO0[1-9] - Instruction trace outputs -> GPIO
stroese13fdf8a2003-09-12 08:55:18 +0000413 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
414 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
415 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
416 * GPIO0[24-27] - UART0 control signal inputs/outputs
417 * GPIO0[28-29] - UART1 data signal input/output
418 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
419 */
wdenkc837dcb2004-01-20 23:12:12 +0000420#define CFG_GPIO0_OSRH 0x40000550
421#define CFG_GPIO0_OSRL 0x00000110
422#define CFG_GPIO0_ISR1H 0x00000000
423#define CFG_GPIO0_ISR1L 0x15555445
424#define CFG_GPIO0_TSRH 0x00000000
425#define CFG_GPIO0_TSRL 0x00000000
426#define CFG_GPIO0_TCR 0xF7FE0014
stroese13fdf8a2003-09-12 08:55:18 +0000427
wdenkc837dcb2004-01-20 23:12:12 +0000428#define CFG_DUART_RST (0x80000000 >> 14)
stroese13fdf8a2003-09-12 08:55:18 +0000429
430/*
431 * Internal Definitions
432 *
433 * Boot Flags
434 */
435#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
436#define BOOTFLAG_WARM 0x02 /* Software reboot */
437
438/*
439 * Default speed selection (cpu_plb_opb_ebc) in mhz.
440 * This value will be set if iic boot eprom is disabled.
441 */
442#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000443#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
444#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000445#endif
446#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000447#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
448#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
stroese13fdf8a2003-09-12 08:55:18 +0000449#endif
450#if 1
wdenkc837dcb2004-01-20 23:12:12 +0000451#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
452#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000453#endif
454
455#endif /* __CONFIG_H */