blob: cbbc62583139c7eb2897add7895523d52b88ba2e [file] [log] [blame]
Shengzhou Liu8d67c362014-03-05 15:04:48 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <command.h>
11#include <netdev.h>
12#include <asm/mmu.h>
13#include <asm/processor.h>
14#include <asm/immap_85xx.h>
15#include <asm/fsl_law.h>
16#include <asm/fsl_serdes.h>
17#include <asm/fsl_portals.h>
18#include <asm/fsl_liodn.h>
19#include <malloc.h>
20#include <fm_eth.h>
21#include <fsl_mdio.h>
22#include <miiphy.h>
23#include <phy.h>
24#include <asm/fsl_dtsec.h>
25#include <asm/fsl_serdes.h>
26
27int board_eth_init(bd_t *bis)
28{
29#if defined(CONFIG_FMAN_ENET)
30 int i, interface;
31 struct memac_mdio_info dtsec_mdio_info;
32 struct memac_mdio_info tgec_mdio_info;
33 struct mii_dev *dev;
34 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
35 u32 srds_s1;
36
37 srds_s1 = in_be32(&gur->rcwsr[4]) &
38 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
39 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
40
41 dtsec_mdio_info.regs =
42 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
43
44 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
45
46 /* Register the 1G MDIO bus */
47 fm_memac_mdio_init(bis, &dtsec_mdio_info);
48
49 tgec_mdio_info.regs =
50 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
51 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
52
53 /* Register the 10G MDIO bus */
54 fm_memac_mdio_init(bis, &tgec_mdio_info);
55
56 /* Set the two on-board RGMII PHY address */
57 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
58 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
59
60 switch (srds_s1) {
61 case 0x66:
62 case 0x6b:
63 fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
64 fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
65 fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
66 fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
67 break;
68 default:
69 printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
70 srds_s1);
71 break;
72 }
73
74 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
75 interface = fm_info_get_enet_if(i);
76 switch (interface) {
77 case PHY_INTERFACE_MODE_RGMII:
78 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
79 fm_info_set_mdio(i, dev);
80 break;
81 default:
82 break;
83 }
84 }
85
86 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
87 switch (fm_info_get_enet_if(i)) {
88 case PHY_INTERFACE_MODE_XGMII:
89 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
90 fm_info_set_mdio(i, dev);
91 break;
92 default:
93 break;
94 }
95 }
96
97 cpu_eth_init(bis);
98#endif /* CONFIG_FMAN_ENET */
99
100 return pci_eth_init(bis);
101}
102
103void fdt_fixup_board_enet(void *fdt)
104{
105 return;
106}