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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 81ec10015181bcf19a190ae4bea94bb1ac8d1da6 / . / board / google / chromebook_link / link.c
blob: 9978e92006d92068ae2b0ce0a8aa6b25fbd91415 [file] [log] [blame]
Simon Glass8ef07572014-11-12 22:42:07 -0700[diff] [blame]1/*
2 * Copyright (C) 2014 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
Simon Glass22e131c2014-11-14 20:56:45 -0700[diff] [blame]8#include <cros_ec.h>
Simon Glass437c2b72014-11-12 22:42:25 -0700[diff] [blame]9#include <asm/gpio.h>
Bin Meng27955732014-12-12 21:05:23 +0800[diff] [blame]10#include <asm/io.h>
11#include <asm/pci.h>
12#include <asm/arch/pch.h>
Simon Glass8ef07572014-11-12 22:42:07 -0700[diff] [blame]13
14int arch_early_init_r(void)
15{
Simon Glass22e131c2014-11-14 20:56:45 -0700[diff] [blame]16 if (cros_ec_board_init())
17 return -1;
18
Simon Glass8ef07572014-11-12 22:42:07 -0700[diff] [blame]19 return 0;
20}
21
Simon Glass437c2b72014-11-12 22:42:25 -0700[diff] [blame]22static const struct pch_gpio_set1 pch_gpio_set1_mode = {
23 .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
24 .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */
25 .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */
26 .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */
27 .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */
28 .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */
29 .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
30 .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
31 .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
32 .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
33 .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
34 .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
35 .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
36 .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
37};
38
39static const struct pch_gpio_set1 pch_gpio_set1_direction = {
40 .gpio0 = GPIO_DIR_INPUT,
41 .gpio3 = GPIO_DIR_INPUT,
42 .gpio5 = GPIO_DIR_INPUT,
43 .gpio7 = GPIO_DIR_INPUT,
44 .gpio8 = GPIO_DIR_INPUT,
45 .gpio9 = GPIO_DIR_INPUT,
46 .gpio10 = GPIO_DIR_INPUT,
47 .gpio11 = GPIO_DIR_INPUT,
48 .gpio12 = GPIO_DIR_INPUT,
49 .gpio14 = GPIO_DIR_INPUT,
50 .gpio15 = GPIO_DIR_INPUT,
51 .gpio21 = GPIO_DIR_INPUT,
52 .gpio24 = GPIO_DIR_OUTPUT,
53 .gpio28 = GPIO_DIR_INPUT,
54};
55
56static const struct pch_gpio_set1 pch_gpio_set1_level = {
57 .gpio1 = GPIO_LEVEL_HIGH,
58 .gpio6 = GPIO_LEVEL_HIGH,
59 .gpio24 = GPIO_LEVEL_LOW,
60};
61
62static const struct pch_gpio_set1 pch_gpio_set1_invert = {
63 .gpio7 = GPIO_INVERT,
64 .gpio8 = GPIO_INVERT,
65 .gpio12 = GPIO_INVERT,
66 .gpio14 = GPIO_INVERT,
67 .gpio15 = GPIO_INVERT,
68};
69
70static const struct pch_gpio_set2 pch_gpio_set2_mode = {
71 .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
72 .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
73 .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
74 .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
75 .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
76 .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
77};
78
79static const struct pch_gpio_set2 pch_gpio_set2_direction = {
80 .gpio36 = GPIO_DIR_OUTPUT,
81 .gpio41 = GPIO_DIR_INPUT,
82 .gpio42 = GPIO_DIR_INPUT,
83 .gpio43 = GPIO_DIR_INPUT,
84 .gpio57 = GPIO_DIR_INPUT,
85 .gpio60 = GPIO_DIR_OUTPUT,
86};
87
88static const struct pch_gpio_set2 pch_gpio_set2_level = {
89 .gpio36 = GPIO_LEVEL_HIGH,
90 .gpio60 = GPIO_LEVEL_HIGH,
91};
92
93static const struct pch_gpio_set3 pch_gpio_set3_mode = {
94};
95
96static const struct pch_gpio_set3 pch_gpio_set3_direction = {
97};
98
99static const struct pch_gpio_set3 pch_gpio_set3_level = {
100};
101
102static const struct pch_gpio_map link_gpio_map = {
103 .set1 = {
104 .mode = &pch_gpio_set1_mode,
105 .direction = &pch_gpio_set1_direction,
106 .level = &pch_gpio_set1_level,
107 .invert = &pch_gpio_set1_invert,
108 },
109 .set2 = {
110 .mode = &pch_gpio_set2_mode,
111 .direction = &pch_gpio_set2_direction,
112 .level = &pch_gpio_set2_level,
113 },
114 .set3 = {
115 .mode = &pch_gpio_set3_mode,
116 .direction = &pch_gpio_set3_direction,
117 .level = &pch_gpio_set3_level,
118 },
119};
120
121int board_early_init_f(void)
122{
123 ich_gpio_set_gpio_map(&link_gpio_map);
124
125 return 0;
126}
Bin Meng27955732014-12-12 21:05:23 +0800[diff] [blame]127
Bin Mengb71eec32014-12-17 15:50:38 +0800[diff] [blame]128void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
Bin Meng27955732014-12-12 21:05:23 +0800[diff] [blame]129{
130 /* GPIO Set 1 */
131 if (gpio->set1.level)
132 outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
133 if (gpio->set1.mode)
134 outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
135 if (gpio->set1.direction)
136 outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
137 if (gpio->set1.reset)
138 outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
139 if (gpio->set1.invert)
140 outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
141 if (gpio->set1.blink)
142 outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
143
144 /* GPIO Set 2 */
145 if (gpio->set2.level)
146 outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
147 if (gpio->set2.mode)
148 outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
149 if (gpio->set2.direction)
150 outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
151 if (gpio->set2.reset)
152 outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
153
154 /* GPIO Set 3 */
155 if (gpio->set3.level)
156 outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
157 if (gpio->set3.mode)
158 outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
159 if (gpio->set3.direction)
160 outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
161 if (gpio->set3.reset)
162 outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
163}