Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2012-2013, Xilinx, Michal Simek |
| 3 | * |
| 4 | * (C) Copyright 2012 |
| 5 | * Joe Hershberger <joe.hershberger@ni.com> |
| 6 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef _ZYNQPL_H_ |
| 11 | #define _ZYNQPL_H_ |
| 12 | |
| 13 | #include <xilinx.h> |
| 14 | |
Michal Simek | 14cfc4f | 2014-03-13 13:07:57 +0100 | [diff] [blame] | 15 | extern struct xilinx_fpga_op zynq_op; |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 16 | |
| 17 | #define XILINX_ZYNQ_7010 0x2 |
Michal Simek | 31993d6 | 2013-09-26 16:39:03 +0200 | [diff] [blame] | 18 | #define XILINX_ZYNQ_7015 0x1b |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 19 | #define XILINX_ZYNQ_7020 0x7 |
| 20 | #define XILINX_ZYNQ_7030 0xc |
| 21 | #define XILINX_ZYNQ_7045 0x11 |
Michal Simek | fd2b10b | 2013-06-17 13:54:07 +0200 | [diff] [blame] | 22 | #define XILINX_ZYNQ_7100 0x16 |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 23 | |
| 24 | /* Device Image Sizes */ |
| 25 | #define XILINX_XC7Z010_SIZE 16669920/8 |
Michal Simek | 31993d6 | 2013-09-26 16:39:03 +0200 | [diff] [blame] | 26 | #define XILINX_XC7Z015_SIZE 28085344/8 |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 27 | #define XILINX_XC7Z020_SIZE 32364512/8 |
| 28 | #define XILINX_XC7Z030_SIZE 47839328/8 |
| 29 | #define XILINX_XC7Z045_SIZE 106571232/8 |
Michal Simek | fd2b10b | 2013-06-17 13:54:07 +0200 | [diff] [blame] | 30 | #define XILINX_XC7Z100_SIZE 139330784/8 |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 31 | |
| 32 | /* Descriptor Macros */ |
| 33 | #define XILINX_XC7Z010_DESC(cookie) \ |
Michal Simek | 14cfc4f | 2014-03-13 13:07:57 +0100 | [diff] [blame] | 34 | { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, &zynq_op, "7z010" } |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 35 | |
Michal Simek | 31993d6 | 2013-09-26 16:39:03 +0200 | [diff] [blame] | 36 | #define XILINX_XC7Z015_DESC(cookie) \ |
Michal Simek | 14cfc4f | 2014-03-13 13:07:57 +0100 | [diff] [blame] | 37 | { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, &zynq_op, "7z015" } |
Michal Simek | 31993d6 | 2013-09-26 16:39:03 +0200 | [diff] [blame] | 38 | |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 39 | #define XILINX_XC7Z020_DESC(cookie) \ |
Michal Simek | 14cfc4f | 2014-03-13 13:07:57 +0100 | [diff] [blame] | 40 | { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, &zynq_op, "7z020" } |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 41 | |
| 42 | #define XILINX_XC7Z030_DESC(cookie) \ |
Michal Simek | 14cfc4f | 2014-03-13 13:07:57 +0100 | [diff] [blame] | 43 | { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, &zynq_op, "7z030" } |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 44 | |
| 45 | #define XILINX_XC7Z045_DESC(cookie) \ |
Michal Simek | 14cfc4f | 2014-03-13 13:07:57 +0100 | [diff] [blame] | 46 | { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, &zynq_op, "7z045" } |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 47 | |
Michal Simek | fd2b10b | 2013-06-17 13:54:07 +0200 | [diff] [blame] | 48 | #define XILINX_XC7Z100_DESC(cookie) \ |
Michal Simek | 14cfc4f | 2014-03-13 13:07:57 +0100 | [diff] [blame] | 49 | { xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, &zynq_op, "7z100" } |
Michal Simek | fd2b10b | 2013-06-17 13:54:07 +0200 | [diff] [blame] | 50 | |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 51 | #endif /* _ZYNQPL_H_ */ |