blob: fea55c61ed7daac57c2da489dec7d173907ac360 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
DrEagle3fe3b4f2014-07-25 21:07:30 +02002/*
3 * Marvell MMC/SD/SDIO driver
4 *
Gerald Kerma2591fbd2014-12-13 21:35:31 +01005 * (C) Copyright 2012-2014
DrEagle3fe3b4f2014-07-25 21:07:30 +02006 * Marvell Semiconductor <www.marvell.com>
7 * Written-by: Maen Suleiman, Gerald Kerma
DrEagle3fe3b4f2014-07-25 21:07:30 +02008 */
9
10#include <common.h>
Jaehoon Chung915ffa52016-07-19 16:33:36 +090011#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
DrEagle3fe3b4f2014-07-25 21:07:30 +020013#include <malloc.h>
Harm Berntsenc689ae02021-03-30 10:19:41 +020014#include <dm.h>
15#include <fdtdec.h>
DrEagle3fe3b4f2014-07-25 21:07:30 +020016#include <part.h>
17#include <mmc.h>
18#include <asm/io.h>
19#include <asm/arch/cpu.h>
Stefan Roese3dc23f72014-10-22 12:13:06 +020020#include <asm/arch/soc.h>
DrEagle3fe3b4f2014-07-25 21:07:30 +020021#include <mvebu_mmc.h>
Harm Berntsenc689ae02021-03-30 10:19:41 +020022#include <dm/device_compat.h>
DrEagle3fe3b4f2014-07-25 21:07:30 +020023
Mario Schuknechtbcd06982014-08-25 14:12:26 +020024#define MVEBU_TARGET_DRAM 0
25
Gerald Kerma28d27b72014-12-13 21:35:32 +010026#define TIMEOUT_DELAY 5*CONFIG_SYS_HZ /* wait 5 seconds */
27
Harm Berntsenc689ae02021-03-30 10:19:41 +020028static inline void *get_regbase(const struct mmc *mmc)
DrEagle3fe3b4f2014-07-25 21:07:30 +020029{
Harm Berntsenc689ae02021-03-30 10:19:41 +020030 struct mvebu_mmc_plat *pdata = mmc->priv;
31
32 return pdata->iobase;
DrEagle3fe3b4f2014-07-25 21:07:30 +020033}
34
Harm Berntsenc689ae02021-03-30 10:19:41 +020035static void mvebu_mmc_write(const struct mmc *mmc, u32 offs, u32 val)
DrEagle3fe3b4f2014-07-25 21:07:30 +020036{
Harm Berntsenc689ae02021-03-30 10:19:41 +020037 writel(val, get_regbase(mmc) + (offs));
DrEagle3fe3b4f2014-07-25 21:07:30 +020038}
39
Harm Berntsenc689ae02021-03-30 10:19:41 +020040static u32 mvebu_mmc_read(const struct mmc *mmc, u32 offs)
DrEagle3fe3b4f2014-07-25 21:07:30 +020041{
Harm Berntsenc689ae02021-03-30 10:19:41 +020042 return readl(get_regbase(mmc) + (offs));
43}
44
45static int mvebu_mmc_setup_data(struct udevice *dev, struct mmc_data *data)
46{
47 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
48 struct mmc *mmc = &pdata->mmc;
DrEagle3fe3b4f2014-07-25 21:07:30 +020049 u32 ctrl_reg;
50
Harm Berntsenc689ae02021-03-30 10:19:41 +020051 dev_dbg(dev, "data %s : blocks=%d blksz=%d\n",
52 (data->flags & MMC_DATA_READ) ? "read" : "write",
53 data->blocks, data->blocksize);
DrEagle3fe3b4f2014-07-25 21:07:30 +020054
55 /* default to maximum timeout */
Harm Berntsenc689ae02021-03-30 10:19:41 +020056 ctrl_reg = mvebu_mmc_read(mmc, SDIO_HOST_CTRL);
DrEagle3fe3b4f2014-07-25 21:07:30 +020057 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
Harm Berntsenc689ae02021-03-30 10:19:41 +020058 mvebu_mmc_write(mmc, SDIO_HOST_CTRL, ctrl_reg);
DrEagle3fe3b4f2014-07-25 21:07:30 +020059
60 if (data->flags & MMC_DATA_READ) {
Harm Berntsenc689ae02021-03-30 10:19:41 +020061 mvebu_mmc_write(mmc, SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
62 mvebu_mmc_write(mmc, SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
DrEagle3fe3b4f2014-07-25 21:07:30 +020063 } else {
Harm Berntsenc689ae02021-03-30 10:19:41 +020064 mvebu_mmc_write(mmc, SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
65 mvebu_mmc_write(mmc, SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
DrEagle3fe3b4f2014-07-25 21:07:30 +020066 }
67
Harm Berntsenc689ae02021-03-30 10:19:41 +020068 mvebu_mmc_write(mmc, SDIO_BLK_COUNT, data->blocks);
69 mvebu_mmc_write(mmc, SDIO_BLK_SIZE, data->blocksize);
DrEagle3fe3b4f2014-07-25 21:07:30 +020070
71 return 0;
72}
73
Harm Berntsenc689ae02021-03-30 10:19:41 +020074static int mvebu_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
DrEagle3fe3b4f2014-07-25 21:07:30 +020075 struct mmc_data *data)
76{
Gerald Kerma28d27b72014-12-13 21:35:32 +010077 ulong start;
DrEagle3fe3b4f2014-07-25 21:07:30 +020078 ushort waittype = 0;
79 ushort resptype = 0;
80 ushort xfertype = 0;
81 ushort resp_indx = 0;
Harm Berntsenc689ae02021-03-30 10:19:41 +020082 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
83 struct mmc *mmc = &pdata->mmc;
DrEagle3fe3b4f2014-07-25 21:07:30 +020084
Harm Berntsenc689ae02021-03-30 10:19:41 +020085 dev_dbg(dev, "cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
86 cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
DrEagle3fe3b4f2014-07-25 21:07:30 +020087
Harm Berntsenc689ae02021-03-30 10:19:41 +020088 dev_dbg(dev, "cmd %d (hw state 0x%04x)\n",
89 cmd->cmdidx, mvebu_mmc_read(mmc, SDIO_HW_STATE));
DrEagle3fe3b4f2014-07-25 21:07:30 +020090
Gerald Kerma28d27b72014-12-13 21:35:32 +010091 /*
92 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
93 * register is sometimes not set before a while when some
94 * "unusual" data block sizes are used (such as with the SWITCH
95 * command), even despite the fact that the XFER_DONE interrupt
96 * was raised. And if another data transfer starts before
97 * this bit comes to good sense (which eventually happens by
98 * itself) then the new transfer simply fails with a timeout.
99 */
Harm Berntsenc689ae02021-03-30 10:19:41 +0200100 if (!(mvebu_mmc_read(mmc, SDIO_HW_STATE) & CMD_FIFO_EMPTY)) {
Gerald Kerma28d27b72014-12-13 21:35:32 +0100101 ushort hw_state, count = 0;
102
103 start = get_timer(0);
104 do {
Harm Berntsenc689ae02021-03-30 10:19:41 +0200105 hw_state = mvebu_mmc_read(mmc, SDIO_HW_STATE);
Gerald Kerma28d27b72014-12-13 21:35:32 +0100106 if ((get_timer(0) - start) > TIMEOUT_DELAY) {
107 printf("%s : FIFO_EMPTY bit missing\n",
Harm Berntsenc689ae02021-03-30 10:19:41 +0200108 dev->name);
Gerald Kerma28d27b72014-12-13 21:35:32 +0100109 break;
110 }
111 count++;
112 } while (!(hw_state & CMD_FIFO_EMPTY));
Harm Berntsenc689ae02021-03-30 10:19:41 +0200113 dev_dbg(dev, "*** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n",
114 hw_state, count, (get_timer(0) - (start)));
DrEagle3fe3b4f2014-07-25 21:07:30 +0200115 }
116
Gerald Kerma02b27392014-12-13 21:35:35 +0100117 /* Clear status */
Harm Berntsenc689ae02021-03-30 10:19:41 +0200118 mvebu_mmc_write(mmc, SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
119 mvebu_mmc_write(mmc, SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200120
121 resptype = SDIO_CMD_INDEX(cmd->cmdidx);
122
123 /* Analyzing resptype/xfertype/waittype for the command */
124 if (cmd->resp_type & MMC_RSP_BUSY)
125 resptype |= SDIO_CMD_RSP_48BUSY;
126 else if (cmd->resp_type & MMC_RSP_136)
127 resptype |= SDIO_CMD_RSP_136;
128 else if (cmd->resp_type & MMC_RSP_PRESENT)
129 resptype |= SDIO_CMD_RSP_48;
130 else
131 resptype |= SDIO_CMD_RSP_NONE;
132
133 if (cmd->resp_type & MMC_RSP_CRC)
134 resptype |= SDIO_CMD_CHECK_CMDCRC;
135
136 if (cmd->resp_type & MMC_RSP_OPCODE)
137 resptype |= SDIO_CMD_INDX_CHECK;
138
139 if (cmd->resp_type & MMC_RSP_PRESENT) {
140 resptype |= SDIO_UNEXPECTED_RESP;
141 waittype |= SDIO_NOR_UNEXP_RSP;
142 }
143
144 if (data) {
Harm Berntsenc689ae02021-03-30 10:19:41 +0200145 int err = mvebu_mmc_setup_data(dev, data);
Gerald Kerma02b27392014-12-13 21:35:35 +0100146
147 if (err) {
Harm Berntsenc689ae02021-03-30 10:19:41 +0200148 dev_dbg(dev, "command DATA error :%x\n", err);
Gerald Kerma02b27392014-12-13 21:35:35 +0100149 return err;
150 }
151
DrEagle3fe3b4f2014-07-25 21:07:30 +0200152 resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
153 xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
154 if (data->flags & MMC_DATA_READ) {
155 xfertype |= SDIO_XFER_MODE_TO_HOST;
156 waittype = SDIO_NOR_DMA_INI;
157 } else {
158 waittype |= SDIO_NOR_XFER_DONE;
159 }
160 } else {
161 waittype |= SDIO_NOR_CMD_DONE;
162 }
163
164 /* Setting cmd arguments */
Harm Berntsenc689ae02021-03-30 10:19:41 +0200165 mvebu_mmc_write(mmc, SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
166 mvebu_mmc_write(mmc, SDIO_ARG_HI, cmd->cmdarg >> 16);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200167
168 /* Setting Xfer mode */
Harm Berntsenc689ae02021-03-30 10:19:41 +0200169 mvebu_mmc_write(mmc, SDIO_XFER_MODE, xfertype);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200170
DrEagle3fe3b4f2014-07-25 21:07:30 +0200171 /* Sending command */
Harm Berntsenc689ae02021-03-30 10:19:41 +0200172 mvebu_mmc_write(mmc, SDIO_CMD, resptype);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200173
Gerald Kerma28d27b72014-12-13 21:35:32 +0100174 start = get_timer(0);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200175
Harm Berntsenc689ae02021-03-30 10:19:41 +0200176 while (!((mvebu_mmc_read(mmc, SDIO_NOR_INTR_STATUS)) & waittype)) {
177 if (mvebu_mmc_read(mmc, SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
178 dev_dbg(dev, "error! cmdidx : %d, err reg: %04x\n",
179 cmd->cmdidx,
180 mvebu_mmc_read(mmc, SDIO_ERR_INTR_STATUS));
181 if (mvebu_mmc_read(mmc, SDIO_ERR_INTR_STATUS) &
Gerald Kermafc0f25f2014-12-13 21:35:33 +0100182 (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) {
Harm Berntsenc689ae02021-03-30 10:19:41 +0200183 dev_dbg(dev, "command READ timed out\n");
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900184 return -ETIMEDOUT;
Gerald Kermafc0f25f2014-12-13 21:35:33 +0100185 }
Harm Berntsenc689ae02021-03-30 10:19:41 +0200186 dev_dbg(dev, "command READ error\n");
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900187 return -ECOMM;
DrEagle3fe3b4f2014-07-25 21:07:30 +0200188 }
189
Gerald Kerma28d27b72014-12-13 21:35:32 +0100190 if ((get_timer(0) - start) > TIMEOUT_DELAY) {
Harm Berntsenc689ae02021-03-30 10:19:41 +0200191 dev_dbg(dev, "command timed out\n");
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900192 return -ETIMEDOUT;
DrEagle3fe3b4f2014-07-25 21:07:30 +0200193 }
194 }
Gerald Kerma28d27b72014-12-13 21:35:32 +0100195
DrEagle3fe3b4f2014-07-25 21:07:30 +0200196 /* Handling response */
197 if (cmd->resp_type & MMC_RSP_136) {
198 uint response[8];
199
200 for (resp_indx = 0; resp_indx < 8; resp_indx++)
Harm Berntsenc689ae02021-03-30 10:19:41 +0200201 response[resp_indx] = mvebu_mmc_read(mmc, SDIO_RSP(resp_indx));
DrEagle3fe3b4f2014-07-25 21:07:30 +0200202
203 cmd->response[0] = ((response[0] & 0x03ff) << 22) |
204 ((response[1] & 0xffff) << 6) |
205 ((response[2] & 0xfc00) >> 10);
206 cmd->response[1] = ((response[2] & 0x03ff) << 22) |
207 ((response[3] & 0xffff) << 6) |
208 ((response[4] & 0xfc00) >> 10);
209 cmd->response[2] = ((response[4] & 0x03ff) << 22) |
210 ((response[5] & 0xffff) << 6) |
211 ((response[6] & 0xfc00) >> 10);
212 cmd->response[3] = ((response[6] & 0x03ff) << 22) |
213 ((response[7] & 0x3fff) << 8);
214 } else if (cmd->resp_type & MMC_RSP_PRESENT) {
215 uint response[3];
216
217 for (resp_indx = 0; resp_indx < 3; resp_indx++)
Harm Berntsenc689ae02021-03-30 10:19:41 +0200218 response[resp_indx] = mvebu_mmc_read(mmc, SDIO_RSP(resp_indx));
DrEagle3fe3b4f2014-07-25 21:07:30 +0200219
220 cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) |
221 ((response[1] & 0xffff) << (14 - 8)) |
222 ((response[0] & 0x03ff) << (30 - 8));
223 cmd->response[1] = ((response[0] & 0xfc00) >> 10);
224 cmd->response[2] = 0;
225 cmd->response[3] = 0;
Gerald Kerma02b27392014-12-13 21:35:35 +0100226 } else {
227 cmd->response[0] = 0;
228 cmd->response[1] = 0;
229 cmd->response[2] = 0;
230 cmd->response[3] = 0;
DrEagle3fe3b4f2014-07-25 21:07:30 +0200231 }
232
Harm Berntsenc689ae02021-03-30 10:19:41 +0200233 dev_dbg(dev, "resp[0x%x] ", cmd->resp_type);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200234 debug("[0x%x] ", cmd->response[0]);
235 debug("[0x%x] ", cmd->response[1]);
236 debug("[0x%x] ", cmd->response[2]);
237 debug("[0x%x] ", cmd->response[3]);
238 debug("\n");
239
Harm Berntsenc689ae02021-03-30 10:19:41 +0200240 if (mvebu_mmc_read(mmc, SDIO_ERR_INTR_STATUS) &
Gerald Kerma02b27392014-12-13 21:35:35 +0100241 (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900242 return -ETIMEDOUT;
Gerald Kerma02b27392014-12-13 21:35:35 +0100243
DrEagle3fe3b4f2014-07-25 21:07:30 +0200244 return 0;
245}
246
Harm Berntsenc689ae02021-03-30 10:19:41 +0200247static void mvebu_mmc_power_up(struct udevice *dev)
DrEagle3fe3b4f2014-07-25 21:07:30 +0200248{
Harm Berntsenc689ae02021-03-30 10:19:41 +0200249 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
250 struct mmc *mmc = &pdata->mmc;
251
252 dev_dbg(dev, "power up\n");
DrEagle3fe3b4f2014-07-25 21:07:30 +0200253
254 /* disable interrupts */
Harm Berntsenc689ae02021-03-30 10:19:41 +0200255 mvebu_mmc_write(mmc, SDIO_NOR_INTR_EN, 0);
256 mvebu_mmc_write(mmc, SDIO_ERR_INTR_EN, 0);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200257
258 /* SW reset */
Harm Berntsenc689ae02021-03-30 10:19:41 +0200259 mvebu_mmc_write(mmc, SDIO_SW_RESET, SDIO_SW_RESET_NOW);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200260
Harm Berntsenc689ae02021-03-30 10:19:41 +0200261 mvebu_mmc_write(mmc, SDIO_XFER_MODE, 0);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200262
263 /* enable status */
Harm Berntsenc689ae02021-03-30 10:19:41 +0200264 mvebu_mmc_write(mmc, SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
265 mvebu_mmc_write(mmc, SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200266
267 /* enable interrupts status */
Harm Berntsenc689ae02021-03-30 10:19:41 +0200268 mvebu_mmc_write(mmc, SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
269 mvebu_mmc_write(mmc, SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200270}
271
Harm Berntsenc689ae02021-03-30 10:19:41 +0200272static void mvebu_mmc_set_clk(struct udevice *dev, unsigned int clock)
DrEagle3fe3b4f2014-07-25 21:07:30 +0200273{
274 unsigned int m;
Harm Berntsenc689ae02021-03-30 10:19:41 +0200275 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
276 struct mmc *mmc = &pdata->mmc;
DrEagle3fe3b4f2014-07-25 21:07:30 +0200277
278 if (clock == 0) {
Harm Berntsenc689ae02021-03-30 10:19:41 +0200279 dev_dbg(dev, "clock off\n");
280 mvebu_mmc_write(mmc, SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
281 mvebu_mmc_write(mmc, SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200282 } else {
283 m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
284 if (m > MVEBU_MMC_BASE_DIV_MAX)
285 m = MVEBU_MMC_BASE_DIV_MAX;
Harm Berntsenc689ae02021-03-30 10:19:41 +0200286 mvebu_mmc_write(mmc, SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
287 dev_dbg(dev, "clock (%d) div : %d\n", clock, m);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200288 }
DrEagle3fe3b4f2014-07-25 21:07:30 +0200289}
290
Harm Berntsenc689ae02021-03-30 10:19:41 +0200291static void mvebu_mmc_set_bus(struct udevice *dev, unsigned int bus)
DrEagle3fe3b4f2014-07-25 21:07:30 +0200292{
Harm Berntsenc689ae02021-03-30 10:19:41 +0200293 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
294 struct mmc *mmc = &pdata->mmc;
DrEagle3fe3b4f2014-07-25 21:07:30 +0200295 u32 ctrl_reg = 0;
296
Harm Berntsenc689ae02021-03-30 10:19:41 +0200297 ctrl_reg = mvebu_mmc_read(mmc, SDIO_HOST_CTRL);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200298 ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
299
300 switch (bus) {
301 case 4:
302 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
303 break;
304 case 1:
305 default:
306 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
307 }
308
309 /* default transfer mode */
310 ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
311 ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
312
313 /* default to maximum timeout */
314 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
Mario Schuknechtbcd06982014-08-25 14:12:26 +0200315 ctrl_reg |= SDIO_HOST_CTRL_TMOUT_EN;
DrEagle3fe3b4f2014-07-25 21:07:30 +0200316
317 ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
318
319 ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
320
Harm Berntsenc689ae02021-03-30 10:19:41 +0200321 dev_dbg(dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
322 (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
323 "push-pull" : "open-drain",
324 (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
325 "4bit-width" : "1bit-width",
326 (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
327 "high-speed" : "");
DrEagle3fe3b4f2014-07-25 21:07:30 +0200328
Harm Berntsenc689ae02021-03-30 10:19:41 +0200329 mvebu_mmc_write(mmc, SDIO_HOST_CTRL, ctrl_reg);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200330}
331
Harm Berntsenc689ae02021-03-30 10:19:41 +0200332static int mvebu_mmc_set_ios(struct udevice *dev)
DrEagle3fe3b4f2014-07-25 21:07:30 +0200333{
Harm Berntsenc689ae02021-03-30 10:19:41 +0200334 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
335 struct mmc *mmc = &pdata->mmc;
336
337 dev_dbg(dev, "bus[%d] clock[%d]\n",
338 mmc->bus_width, mmc->clock);
339 mvebu_mmc_set_bus(dev, mmc->bus_width);
340 mvebu_mmc_set_clk(dev, mmc->clock);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900341
342 return 0;
DrEagle3fe3b4f2014-07-25 21:07:30 +0200343}
344
Mario Schuknechtbcd06982014-08-25 14:12:26 +0200345/*
346 * Set window register.
347 */
Harm Berntsenc689ae02021-03-30 10:19:41 +0200348static void mvebu_window_setup(const struct mmc *mmc)
Mario Schuknechtbcd06982014-08-25 14:12:26 +0200349{
350 int i;
351
352 for (i = 0; i < 4; i++) {
Harm Berntsenc689ae02021-03-30 10:19:41 +0200353 mvebu_mmc_write(mmc, WINDOW_CTRL(i), 0);
354 mvebu_mmc_write(mmc, WINDOW_BASE(i), 0);
Mario Schuknechtbcd06982014-08-25 14:12:26 +0200355 }
356 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
357 u32 size, base, attrib;
358
359 /* Enable DRAM bank */
360 switch (i) {
361 case 0:
362 attrib = KWCPU_ATTR_DRAM_CS0;
363 break;
364 case 1:
365 attrib = KWCPU_ATTR_DRAM_CS1;
366 break;
367 case 2:
368 attrib = KWCPU_ATTR_DRAM_CS2;
369 break;
370 case 3:
371 attrib = KWCPU_ATTR_DRAM_CS3;
372 break;
373 default:
374 /* invalide bank, disable access */
375 attrib = 0;
376 break;
377 }
378
379 size = gd->bd->bi_dram[i].size;
380 base = gd->bd->bi_dram[i].start;
381 if (size && attrib) {
Harm Berntsenc689ae02021-03-30 10:19:41 +0200382 mvebu_mmc_write(mmc, WINDOW_CTRL(i),
Mario Schuknechtbcd06982014-08-25 14:12:26 +0200383 MVCPU_WIN_CTRL_DATA(size,
384 MVEBU_TARGET_DRAM,
385 attrib,
386 MVCPU_WIN_ENABLE));
387 } else {
Harm Berntsenc689ae02021-03-30 10:19:41 +0200388 mvebu_mmc_write(mmc, WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
Mario Schuknechtbcd06982014-08-25 14:12:26 +0200389 }
Harm Berntsenc689ae02021-03-30 10:19:41 +0200390 mvebu_mmc_write(mmc, WINDOW_BASE(i), base);
Mario Schuknechtbcd06982014-08-25 14:12:26 +0200391 }
392}
393
Harm Berntsenc689ae02021-03-30 10:19:41 +0200394static int mvebu_mmc_initialize(struct udevice *dev)
DrEagle3fe3b4f2014-07-25 21:07:30 +0200395{
Harm Berntsenc689ae02021-03-30 10:19:41 +0200396 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
397 struct mmc *mmc = &pdata->mmc;
398
399 dev_dbg(dev, "%s\n", __func__);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200400
401 /*
402 * Setting host parameters
403 * Initial Host Ctrl : Timeout : max , Normal Speed mode,
404 * 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line
405 */
Harm Berntsenc689ae02021-03-30 10:19:41 +0200406 mvebu_mmc_write(mmc, SDIO_HOST_CTRL,
DrEagle3fe3b4f2014-07-25 21:07:30 +0200407 SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
408 SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
409 SDIO_HOST_CTRL_BIG_ENDIAN |
410 SDIO_HOST_CTRL_PUSH_PULL_EN |
411 SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
412
Harm Berntsenc689ae02021-03-30 10:19:41 +0200413 mvebu_mmc_write(mmc, SDIO_CLK_CTRL, 0);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200414
415 /* enable status */
Harm Berntsenc689ae02021-03-30 10:19:41 +0200416 mvebu_mmc_write(mmc, SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
417 mvebu_mmc_write(mmc, SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200418
419 /* disable interrupts */
Harm Berntsenc689ae02021-03-30 10:19:41 +0200420 mvebu_mmc_write(mmc, SDIO_NOR_INTR_EN, 0);
421 mvebu_mmc_write(mmc, SDIO_ERR_INTR_EN, 0);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200422
Harm Berntsenc689ae02021-03-30 10:19:41 +0200423 mvebu_window_setup(mmc);
Mario Schuknechtbcd06982014-08-25 14:12:26 +0200424
DrEagle3fe3b4f2014-07-25 21:07:30 +0200425 /* SW reset */
Harm Berntsenc689ae02021-03-30 10:19:41 +0200426 mvebu_mmc_write(mmc, SDIO_SW_RESET, SDIO_SW_RESET_NOW);
DrEagle3fe3b4f2014-07-25 21:07:30 +0200427
DrEagle3fe3b4f2014-07-25 21:07:30 +0200428 return 0;
429}
430
Harm Berntsenc689ae02021-03-30 10:19:41 +0200431static int mvebu_mmc_of_to_plat(struct udevice *dev)
DrEagle3fe3b4f2014-07-25 21:07:30 +0200432{
Harm Berntsenc689ae02021-03-30 10:19:41 +0200433 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
434 fdt_addr_t addr;
DrEagle3fe3b4f2014-07-25 21:07:30 +0200435
Harm Berntsenc689ae02021-03-30 10:19:41 +0200436 addr = dev_read_addr(dev);
437 if (addr == FDT_ADDR_T_NONE)
438 return -EINVAL;
DrEagle3fe3b4f2014-07-25 21:07:30 +0200439
Harm Berntsenc689ae02021-03-30 10:19:41 +0200440 pdata->iobase = (void *)addr;
DrEagle3fe3b4f2014-07-25 21:07:30 +0200441
442 return 0;
443}
Harm Berntsenc689ae02021-03-30 10:19:41 +0200444
445static int mvebu_mmc_probe(struct udevice *dev)
446{
447 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
448 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
449 struct mmc *mmc = &pdata->mmc;
450 struct mmc_config *cfg = &pdata->cfg;
451
452 cfg->name = dev->name;
453 cfg->f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX;
454 cfg->f_max = MVEBU_MMC_CLOCKRATE_MAX;
455 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
456 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
457 cfg->part_type = PART_TYPE_DOS;
458 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
459
460 mmc->cfg = cfg;
461 mmc->priv = pdata;
462 mmc->dev = dev;
463 upriv->mmc = mmc;
464
465 mvebu_mmc_power_up(dev);
466 mvebu_mmc_initialize(dev);
467
468 return 0;
469}
470
471static const struct dm_mmc_ops mvebu_dm_mmc_ops = {
472 .send_cmd = mvebu_mmc_send_cmd,
473 .set_ios = mvebu_mmc_set_ios,
474};
475
476static int mvebu_mmc_bind(struct udevice *dev)
477{
478 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
479
480 return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
481}
482
483static const struct udevice_id mvebu_mmc_match[] = {
484 { .compatible = "marvell,orion-sdio" },
485 { /* sentinel */ }
486};
487
488U_BOOT_DRIVER(mvebu_mmc) = {
489 .name = "mvebu_mmc",
490 .id = UCLASS_MMC,
491 .of_match = mvebu_mmc_match,
492 .ops = &mvebu_dm_mmc_ops,
493 .probe = mvebu_mmc_probe,
494 .bind = mvebu_mmc_bind,
495 .of_to_plat = mvebu_mmc_of_to_plat,
496 .plat_auto = sizeof(struct mvebu_mmc_plat),
497};