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Simon Glass6f967852016-05-05 07:28:12 -06001/*
2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
3 * applies to AT91SAM9G45, AT91SAM9M10,
4 * AT91SAM9G46, AT91SAM9M11 SoC
5 *
6 * Copyright (C) 2011 Atmel,
7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12#include "skeleton.dtsi"
13#include <dt-bindings/dma/at91.h>
14#include <dt-bindings/pinctrl/at91.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/clock/at91.h>
18
19/ {
20 model = "Atmel AT91SAM9G45 family SoC";
21 compatible = "atmel,at91sam9g45";
22 interrupt-parent = <&aic>;
23
24 aliases {
25 serial0 = &dbgu;
26 serial1 = &usart0;
27 serial2 = &usart1;
28 serial3 = &usart2;
29 serial4 = &usart3;
30 gpio0 = &pioA;
31 gpio1 = &pioB;
32 gpio2 = &pioC;
33 gpio3 = &pioD;
34 gpio4 = &pioE;
35 tcb0 = &tcb0;
36 tcb1 = &tcb1;
37 i2c0 = &i2c0;
38 i2c1 = &i2c1;
39 ssc0 = &ssc0;
40 ssc1 = &ssc1;
41 pwm0 = &pwm0;
42 };
43 cpus {
44 #address-cells = <0>;
45 #size-cells = <0>;
46
47 cpu {
48 compatible = "arm,arm926ej-s";
49 device_type = "cpu";
50 };
51 };
52
53 memory {
54 reg = <0x70000000 0x10000000>;
55 };
56
57 clocks {
58 slow_xtal: slow_xtal {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <0>;
62 };
63
64 main_xtal: main_xtal {
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <0>;
68 };
69
70 adc_op_clk: adc_op_clk{
71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <300000>;
74 };
75 };
76
77 sram: sram@00300000 {
78 compatible = "mmio-sram";
79 reg = <0x00300000 0x10000>;
80 };
81
82 ahb {
83 compatible = "simple-bus";
84 #address-cells = <1>;
85 #size-cells = <1>;
86 ranges;
Wenyou Yangeb6f87c2017-04-18 13:49:36 +080087 u-boot,dm-pre-reloc;
Simon Glass6f967852016-05-05 07:28:12 -060088
89 apb {
90 compatible = "simple-bus";
91 #address-cells = <1>;
92 #size-cells = <1>;
93 ranges;
Wenyou Yangeb6f87c2017-04-18 13:49:36 +080094 u-boot,dm-pre-reloc;
Simon Glass6f967852016-05-05 07:28:12 -060095
96 aic: interrupt-controller@fffff000 {
97 #interrupt-cells = <3>;
98 compatible = "atmel,at91rm9200-aic";
99 interrupt-controller;
100 reg = <0xfffff000 0x200>;
101 atmel,external-irqs = <31>;
102 };
103
104 ramc0: ramc@ffffe400 {
105 compatible = "atmel,at91sam9g45-ddramc";
106 reg = <0xffffe400 0x200>;
107 clocks = <&ddrck>;
108 clock-names = "ddrck";
109 };
110
111 ramc1: ramc@ffffe600 {
112 compatible = "atmel,at91sam9g45-ddramc";
113 reg = <0xffffe600 0x200>;
114 clocks = <&ddrck>;
115 clock-names = "ddrck";
116 };
117
118 pmc: pmc@fffffc00 {
119 compatible = "atmel,at91sam9g45-pmc", "syscon";
120 reg = <0xfffffc00 0x100>;
121 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
122 interrupt-controller;
123 #address-cells = <1>;
124 #size-cells = <0>;
125 #interrupt-cells = <1>;
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800126 u-boot,dm-pre-reloc;
Simon Glass6f967852016-05-05 07:28:12 -0600127
128 main_osc: main_osc {
129 compatible = "atmel,at91rm9200-clk-main-osc";
130 #clock-cells = <0>;
131 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
132 clocks = <&main_xtal>;
133 };
134
135 main: mainck {
136 compatible = "atmel,at91rm9200-clk-main";
137 #clock-cells = <0>;
138 clocks = <&main_osc>;
139 };
140
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800141 plla: pllack@0 {
Simon Glass6f967852016-05-05 07:28:12 -0600142 compatible = "atmel,at91rm9200-clk-pll";
143 #clock-cells = <0>;
144 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
145 clocks = <&main>;
146 reg = <0>;
147 atmel,clk-input-range = <2000000 32000000>;
148 #atmel,pll-clk-output-range-cells = <4>;
149 atmel,pll-clk-output-ranges = <745000000 800000000 0 0
150 695000000 750000000 1 0
151 645000000 700000000 2 0
152 595000000 650000000 3 0
153 545000000 600000000 0 1
154 495000000 555000000 1 1
155 445000000 500000000 2 1
156 400000000 450000000 3 1>;
157 };
158
159 plladiv: plladivck {
160 compatible = "atmel,at91sam9x5-clk-plldiv";
161 #clock-cells = <0>;
162 clocks = <&plla>;
163 };
164
165 utmi: utmick {
166 compatible = "atmel,at91sam9x5-clk-utmi";
167 #clock-cells = <0>;
168 interrupts-extended = <&pmc AT91_PMC_LOCKU>;
169 clocks = <&main>;
170 };
171
172 mck: masterck {
173 compatible = "atmel,at91rm9200-clk-master";
174 #clock-cells = <0>;
175 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
176 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
177 atmel,clk-output-range = <0 133333333>;
178 atmel,clk-divisors = <1 2 4 3>;
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800179 u-boot,dm-pre-reloc;
Simon Glass6f967852016-05-05 07:28:12 -0600180 };
181
182 usb: usbck {
183 compatible = "atmel,at91sam9x5-clk-usb";
184 #clock-cells = <0>;
185 clocks = <&plladiv>, <&utmi>;
186 };
187
188 prog: progck {
189 compatible = "atmel,at91sam9g45-clk-programmable";
190 #address-cells = <1>;
191 #size-cells = <0>;
192 interrupt-parent = <&pmc>;
193 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
194
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800195 prog0: prog@0 {
Simon Glass6f967852016-05-05 07:28:12 -0600196 #clock-cells = <0>;
197 reg = <0>;
198 interrupts = <AT91_PMC_PCKRDY(0)>;
199 };
200
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800201 prog1: prog@1 {
Simon Glass6f967852016-05-05 07:28:12 -0600202 #clock-cells = <0>;
203 reg = <1>;
204 interrupts = <AT91_PMC_PCKRDY(1)>;
205 };
206 };
207
208 systemck {
209 compatible = "atmel,at91rm9200-clk-system";
210 #address-cells = <1>;
211 #size-cells = <0>;
212
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800213 ddrck: ddrck@2 {
Simon Glass6f967852016-05-05 07:28:12 -0600214 #clock-cells = <0>;
215 reg = <2>;
216 clocks = <&mck>;
217 };
218
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800219 uhpck: uhpck@6 {
Simon Glass6f967852016-05-05 07:28:12 -0600220 #clock-cells = <0>;
221 reg = <6>;
222 clocks = <&usb>;
223 };
224
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800225 pck0: pck0@8 {
Simon Glass6f967852016-05-05 07:28:12 -0600226 #clock-cells = <0>;
227 reg = <8>;
228 clocks = <&prog0>;
229 };
230
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800231 pck1: pck1@9 {
Simon Glass6f967852016-05-05 07:28:12 -0600232 #clock-cells = <0>;
233 reg = <9>;
234 clocks = <&prog1>;
235 };
236 };
237
238 periphck {
239 compatible = "atmel,at91rm9200-clk-peripheral";
240 #address-cells = <1>;
241 #size-cells = <0>;
242 clocks = <&mck>;
243
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800244 pioA_clk: pioA_clk@2 {
Simon Glass6f967852016-05-05 07:28:12 -0600245 #clock-cells = <0>;
246 reg = <2>;
247 };
248
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800249 pioB_clk: pioB_clk@3 {
Simon Glass6f967852016-05-05 07:28:12 -0600250 #clock-cells = <0>;
251 reg = <3>;
252 };
253
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800254 pioC_clk: pioC_clk@4 {
Simon Glass6f967852016-05-05 07:28:12 -0600255 #clock-cells = <0>;
256 reg = <4>;
257 };
258
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800259 pioDE_clk: pioDE_clk@5 {
Simon Glass6f967852016-05-05 07:28:12 -0600260 #clock-cells = <0>;
261 reg = <5>;
262 };
263
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800264 trng_clk: trng_clk@6 {
Simon Glass6f967852016-05-05 07:28:12 -0600265 #clock-cells = <0>;
266 reg = <6>;
267 };
268
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800269 usart0_clk: usart0_clk@7 {
Simon Glass6f967852016-05-05 07:28:12 -0600270 #clock-cells = <0>;
271 reg = <7>;
272 };
273
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800274 usart1_clk: usart1_clk@8 {
Simon Glass6f967852016-05-05 07:28:12 -0600275 #clock-cells = <0>;
276 reg = <8>;
277 };
278
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800279 usart2_clk: usart2_clk@9 {
Simon Glass6f967852016-05-05 07:28:12 -0600280 #clock-cells = <0>;
281 reg = <9>;
282 };
283
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800284 usart3_clk: usart3_clk@10 {
Simon Glass6f967852016-05-05 07:28:12 -0600285 #clock-cells = <0>;
286 reg = <10>;
287 };
288
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800289 mci0_clk: mci0_clk@11 {
Simon Glass6f967852016-05-05 07:28:12 -0600290 #clock-cells = <0>;
291 reg = <11>;
292 };
293
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800294 twi0_clk: twi0_clk@12 {
Simon Glass6f967852016-05-05 07:28:12 -0600295 #clock-cells = <0>;
296 reg = <12>;
297 };
298
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800299 twi1_clk: twi1_clk@13 {
Simon Glass6f967852016-05-05 07:28:12 -0600300 #clock-cells = <0>;
301 reg = <13>;
302 };
303
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800304 spi0_clk: spi0_clk@14 {
Simon Glass6f967852016-05-05 07:28:12 -0600305 #clock-cells = <0>;
306 reg = <14>;
307 };
308
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800309 spi1_clk: spi1_clk@15 {
Simon Glass6f967852016-05-05 07:28:12 -0600310 #clock-cells = <0>;
311 reg = <15>;
312 };
313
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800314 ssc0_clk: ssc0_clk@16 {
Simon Glass6f967852016-05-05 07:28:12 -0600315 #clock-cells = <0>;
316 reg = <16>;
317 };
318
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800319 ssc1_clk: ssc1_clk@17 {
Simon Glass6f967852016-05-05 07:28:12 -0600320 #clock-cells = <0>;
321 reg = <17>;
322 };
323
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800324 tcb0_clk: tcb0_clk@18 {
Simon Glass6f967852016-05-05 07:28:12 -0600325 #clock-cells = <0>;
326 reg = <18>;
327 };
328
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800329 pwm_clk: pwm_clk@19 {
Simon Glass6f967852016-05-05 07:28:12 -0600330 #clock-cells = <0>;
331 reg = <19>;
332 };
333
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800334 adc_clk: adc_clk@20 {
Simon Glass6f967852016-05-05 07:28:12 -0600335 #clock-cells = <0>;
336 reg = <20>;
337 };
338
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800339 dma0_clk: dma0_clk@21 {
Simon Glass6f967852016-05-05 07:28:12 -0600340 #clock-cells = <0>;
341 reg = <21>;
342 };
343
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800344 uhphs_clk: uhphs_clk@22 {
Simon Glass6f967852016-05-05 07:28:12 -0600345 #clock-cells = <0>;
346 reg = <22>;
347 };
348
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800349 lcd_clk: lcd_clk@23 {
Simon Glass6f967852016-05-05 07:28:12 -0600350 #clock-cells = <0>;
351 reg = <23>;
352 };
353
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800354 ac97_clk: ac97_clk@24 {
Simon Glass6f967852016-05-05 07:28:12 -0600355 #clock-cells = <0>;
356 reg = <24>;
357 };
358
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800359 macb0_clk: macb0_clk@25 {
Simon Glass6f967852016-05-05 07:28:12 -0600360 #clock-cells = <0>;
361 reg = <25>;
362 };
363
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800364 isi_clk: isi_clk@26 {
Simon Glass6f967852016-05-05 07:28:12 -0600365 #clock-cells = <0>;
366 reg = <26>;
367 };
368
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800369 udphs_clk: udphs_clk@27 {
Simon Glass6f967852016-05-05 07:28:12 -0600370 #clock-cells = <0>;
371 reg = <27>;
372 };
373
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800374 aestdessha_clk: aestdessha_clk@28 {
Simon Glass6f967852016-05-05 07:28:12 -0600375 #clock-cells = <0>;
376 reg = <28>;
377 };
378
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800379 mci1_clk: mci1_clk@29 {
Simon Glass6f967852016-05-05 07:28:12 -0600380 #clock-cells = <0>;
381 reg = <29>;
382 };
383
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800384 vdec_clk: vdec_clk@30 {
Simon Glass6f967852016-05-05 07:28:12 -0600385 #clock-cells = <0>;
386 reg = <30>;
387 };
388 };
389 };
390
391 rstc@fffffd00 {
392 compatible = "atmel,at91sam9g45-rstc";
393 reg = <0xfffffd00 0x10>;
394 clocks = <&clk32k>;
395 };
396
397 pit: timer@fffffd30 {
398 compatible = "atmel,at91sam9260-pit";
399 reg = <0xfffffd30 0xf>;
400 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
401 clocks = <&mck>;
402 };
403
404
405 shdwc@fffffd10 {
406 compatible = "atmel,at91sam9rl-shdwc";
407 reg = <0xfffffd10 0x10>;
408 clocks = <&clk32k>;
409 };
410
411 tcb0: timer@fff7c000 {
412 compatible = "atmel,at91rm9200-tcb";
413 reg = <0xfff7c000 0x100>;
414 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
415 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
416 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
417 };
418
419 tcb1: timer@fffd4000 {
420 compatible = "atmel,at91rm9200-tcb";
421 reg = <0xfffd4000 0x100>;
422 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
423 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
424 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
425 };
426
427 dma: dma-controller@ffffec00 {
428 compatible = "atmel,at91sam9g45-dma";
429 reg = <0xffffec00 0x200>;
430 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
431 #dma-cells = <2>;
432 clocks = <&dma0_clk>;
433 clock-names = "dma_clk";
434 };
435
436 pinctrl@fffff200 {
437 #address-cells = <1>;
438 #size-cells = <1>;
439 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
440 ranges = <0xfffff200 0xfffff200 0xa00>;
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800441 reg = <0xfffff200 0x200
442 0xfffff400 0x200
443 0xfffff600 0x200
444 0xfffff800 0x200
445 0xfffffa00 0x200
446 >;
447 u-boot,dm-pre-reloc;
Simon Glass6f967852016-05-05 07:28:12 -0600448
449 atmel,mux-mask = <
450 /* A B */
451 0xffffffff 0xffc003ff /* pioA */
452 0xffffffff 0x800f8f00 /* pioB */
453 0xffffffff 0x00000e00 /* pioC */
454 0xffffffff 0xff0c1381 /* pioD */
455 0xffffffff 0x81ffff81 /* pioE */
456 >;
457
458 /* shared pinctrl settings */
459 adc0 {
460 pinctrl_adc0_adtrg: adc0_adtrg {
461 atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
462 };
463 pinctrl_adc0_ad0: adc0_ad0 {
464 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
465 };
466 pinctrl_adc0_ad1: adc0_ad1 {
467 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
468 };
469 pinctrl_adc0_ad2: adc0_ad2 {
470 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
471 };
472 pinctrl_adc0_ad3: adc0_ad3 {
473 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
474 };
475 pinctrl_adc0_ad4: adc0_ad4 {
476 atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
477 };
478 pinctrl_adc0_ad5: adc0_ad5 {
479 atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
480 };
481 pinctrl_adc0_ad6: adc0_ad6 {
482 atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
483 };
484 pinctrl_adc0_ad7: adc0_ad7 {
485 atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
486 };
487 };
488
489 dbgu {
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800490 u-boot,dm-pre-reloc;
Simon Glass6f967852016-05-05 07:28:12 -0600491 pinctrl_dbgu: dbgu-0 {
492 atmel,pins =
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800493 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
494 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
Simon Glass6f967852016-05-05 07:28:12 -0600495 };
496 };
497
498 i2c0 {
499 pinctrl_i2c0: i2c0-0 {
500 atmel,pins =
501 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */
502 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */
503 };
504 };
505
506 i2c1 {
507 pinctrl_i2c1: i2c1-0 {
508 atmel,pins =
509 <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */
510 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */
511 };
512 };
513
514 isi {
515 pinctrl_isi_data_0_7: isi-0-data-0-7 {
516 atmel,pins =
517 <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
518 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
519 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
520 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
521 AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
522 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
523 AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
524 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
525 AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
526 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
527 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
528 };
529
530 pinctrl_isi_data_8_9: isi-0-data-8-9 {
531 atmel,pins =
532 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
533 AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D9 */
534 };
535
536 pinctrl_isi_data_10_11: isi-0-data-10-11 {
537 atmel,pins =
538 <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
539 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D11 */
540 };
541 };
542
543 usart0 {
544 pinctrl_usart0: usart0-0 {
545 atmel,pins =
546 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */
547 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
548 };
549
550 pinctrl_usart0_rts: usart0_rts-0 {
551 atmel,pins =
552 <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
553 };
554
555 pinctrl_usart0_cts: usart0_cts-0 {
556 atmel,pins =
557 <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
558 };
559 };
560
561 uart1 {
562 pinctrl_usart1: usart1-0 {
563 atmel,pins =
564 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
565 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
566 };
567
568 pinctrl_usart1_rts: usart1_rts-0 {
569 atmel,pins =
570 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
571 };
572
573 pinctrl_usart1_cts: usart1_cts-0 {
574 atmel,pins =
575 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
576 };
577 };
578
579 usart2 {
580 pinctrl_usart2: usart2-0 {
581 atmel,pins =
582 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
583 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
584 };
585
586 pinctrl_usart2_rts: usart2_rts-0 {
587 atmel,pins =
588 <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */
589 };
590
591 pinctrl_usart2_cts: usart2_cts-0 {
592 atmel,pins =
593 <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
594 };
595 };
596
597 usart3 {
598 pinctrl_usart3: usart3-0 {
599 atmel,pins =
600 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
601 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
602 };
603
604 pinctrl_usart3_rts: usart3_rts-0 {
605 atmel,pins =
606 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
607 };
608
609 pinctrl_usart3_cts: usart3_cts-0 {
610 atmel,pins =
611 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
612 };
613 };
614
615 nand {
616 pinctrl_nand: nand-0 {
617 atmel,pins =
618 <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/
619 AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
620 };
621 };
622
623 macb {
624 pinctrl_macb_rmii: macb_rmii-0 {
625 atmel,pins =
626 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
627 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
628 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
629 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
630 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
631 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
632 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
633 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
634 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
635 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
636 };
637
638 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
639 atmel,pins =
640 <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */
641 AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */
642 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */
643 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */
644 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
645 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
646 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */
647 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
648 };
649 };
650
651 mmc0 {
652 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
653 atmel,pins =
654 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
655 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
656 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */
657 };
658
659 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
660 atmel,pins =
661 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
662 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
663 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
664 };
665
666 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
667 atmel,pins =
668 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
669 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
670 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
671 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */
672 };
673 };
674
675 mmc1 {
676 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
677 atmel,pins =
678 <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */
679 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */
680 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
681 };
682
683 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
684 atmel,pins =
685 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
686 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */
687 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */
688 };
689
690 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
691 atmel,pins =
692 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */
693 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
694 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */
695 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */
696 };
697 };
698
699 ssc0 {
700 pinctrl_ssc0_tx: ssc0_tx-0 {
701 atmel,pins =
702 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
703 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */
704 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */
705 };
706
707 pinctrl_ssc0_rx: ssc0_rx-0 {
708 atmel,pins =
709 <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */
710 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */
711 AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */
712 };
713 };
714
715 ssc1 {
716 pinctrl_ssc1_tx: ssc1_tx-0 {
717 atmel,pins =
718 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */
719 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */
720 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
721 };
722
723 pinctrl_ssc1_rx: ssc1_rx-0 {
724 atmel,pins =
725 <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */
726 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */
727 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
728 };
729 };
730
731 spi0 {
732 pinctrl_spi0: spi0-0 {
733 atmel,pins =
734 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
735 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */
736 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */
737 };
738 };
739
740 spi1 {
741 pinctrl_spi1: spi1-0 {
742 atmel,pins =
743 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */
744 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */
745 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
746 };
747 };
748
749 tcb0 {
750 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
751 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
752 };
753
754 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
755 atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
756 };
757
758 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
759 atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
760 };
761
762 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
763 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
764 };
765
766 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
767 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
768 };
769
770 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
771 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
772 };
773
774 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
775 atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
776 };
777
778 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
779 atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
780 };
781
782 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
783 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
784 };
785 };
786
787 tcb1 {
788 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
789 atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
790 };
791
792 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
793 atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
794 };
795
796 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
797 atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
798 };
799
800 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
801 atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
802 };
803
804 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
805 atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
806 };
807
808 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
809 atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
810 };
811
812 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
813 atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
814 };
815
816 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
817 atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
818 };
819
820 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
821 atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
822 };
823 };
824
825 fb {
826 pinctrl_fb: fb-0 {
827 atmel,pins =
828 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */
829 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */
830 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */
831 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */
832 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */
833 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */
834 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */
835 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */
836 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */
837 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */
838 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */
839 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */
840 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */
841 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */
842 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */
843 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */
844 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */
845 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */
846 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */
847 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */
848 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
849 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */
850 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
851 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
852 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
853 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
854 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
855 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
856 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
857 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
858 };
859 };
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800860 };
Simon Glass6f967852016-05-05 07:28:12 -0600861
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800862 pioA: gpio@fffff200 {
863 compatible = "atmel,at91rm9200-gpio";
864 reg = <0xfffff200 0x200>;
865 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
866 #gpio-cells = <2>;
867 gpio-controller;
868 interrupt-controller;
869 #interrupt-cells = <2>;
870 clocks = <&pioA_clk>;
871 };
Simon Glass6f967852016-05-05 07:28:12 -0600872
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800873 pioB: gpio@fffff400 {
874 compatible = "atmel,at91rm9200-gpio";
875 reg = <0xfffff400 0x200>;
876 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
877 #gpio-cells = <2>;
878 gpio-controller;
879 interrupt-controller;
880 #interrupt-cells = <2>;
881 clocks = <&pioB_clk>;
882 };
Simon Glass6f967852016-05-05 07:28:12 -0600883
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800884 pioC: gpio@fffff600 {
885 compatible = "atmel,at91rm9200-gpio";
886 reg = <0xfffff600 0x200>;
887 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
888 #gpio-cells = <2>;
889 gpio-controller;
890 interrupt-controller;
891 #interrupt-cells = <2>;
892 clocks = <&pioC_clk>;
893 };
Simon Glass6f967852016-05-05 07:28:12 -0600894
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800895 pioD: gpio@fffff800 {
896 compatible = "atmel,at91rm9200-gpio";
897 reg = <0xfffff800 0x200>;
898 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
899 #gpio-cells = <2>;
900 gpio-controller;
901 interrupt-controller;
902 #interrupt-cells = <2>;
903 clocks = <&pioDE_clk>;
904 };
Simon Glass6f967852016-05-05 07:28:12 -0600905
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800906 pioE: gpio@fffffa00 {
907 compatible = "atmel,at91rm9200-gpio";
908 reg = <0xfffffa00 0x200>;
909 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
910 #gpio-cells = <2>;
911 gpio-controller;
912 interrupt-controller;
913 #interrupt-cells = <2>;
914 clocks = <&pioDE_clk>;
Simon Glass6f967852016-05-05 07:28:12 -0600915 };
916
917 dbgu: serial@ffffee00 {
918 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
919 reg = <0xffffee00 0x200>;
920 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
921 pinctrl-names = "default";
922 pinctrl-0 = <&pinctrl_dbgu>;
923 clocks = <&mck>;
924 clock-names = "usart";
925 status = "disabled";
926 };
927
928 usart0: serial@fff8c000 {
929 compatible = "atmel,at91sam9260-usart";
930 reg = <0xfff8c000 0x200>;
931 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
932 atmel,use-dma-rx;
933 atmel,use-dma-tx;
934 pinctrl-names = "default";
935 pinctrl-0 = <&pinctrl_usart0>;
936 clocks = <&usart0_clk>;
937 clock-names = "usart";
938 status = "disabled";
939 };
940
941 usart1: serial@fff90000 {
942 compatible = "atmel,at91sam9260-usart";
943 reg = <0xfff90000 0x200>;
944 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
945 atmel,use-dma-rx;
946 atmel,use-dma-tx;
947 pinctrl-names = "default";
948 pinctrl-0 = <&pinctrl_usart1>;
949 clocks = <&usart1_clk>;
950 clock-names = "usart";
951 status = "disabled";
952 };
953
954 usart2: serial@fff94000 {
955 compatible = "atmel,at91sam9260-usart";
956 reg = <0xfff94000 0x200>;
957 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
958 atmel,use-dma-rx;
959 atmel,use-dma-tx;
960 pinctrl-names = "default";
961 pinctrl-0 = <&pinctrl_usart2>;
962 clocks = <&usart2_clk>;
963 clock-names = "usart";
964 status = "disabled";
965 };
966
967 usart3: serial@fff98000 {
968 compatible = "atmel,at91sam9260-usart";
969 reg = <0xfff98000 0x200>;
970 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
971 atmel,use-dma-rx;
972 atmel,use-dma-tx;
973 pinctrl-names = "default";
974 pinctrl-0 = <&pinctrl_usart3>;
975 clocks = <&usart3_clk>;
976 clock-names = "usart";
977 status = "disabled";
978 };
979
980 macb0: ethernet@fffbc000 {
981 compatible = "cdns,at91sam9260-macb", "cdns,macb";
982 reg = <0xfffbc000 0x100>;
983 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
984 pinctrl-names = "default";
985 pinctrl-0 = <&pinctrl_macb_rmii>;
986 clocks = <&macb0_clk>, <&macb0_clk>;
987 clock-names = "hclk", "pclk";
988 status = "disabled";
989 };
990
991 trng@fffcc000 {
992 compatible = "atmel,at91sam9g45-trng";
Wenyou Yangeb6f87c2017-04-18 13:49:36 +0800993 reg = <0xfffcc000 0x100>;
Simon Glass6f967852016-05-05 07:28:12 -0600994 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
995 clocks = <&trng_clk>;
996 };
997
998 i2c0: i2c@fff84000 {
999 compatible = "atmel,at91sam9g10-i2c";
1000 reg = <0xfff84000 0x100>;
1001 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&pinctrl_i2c0>;
1004 #address-cells = <1>;
1005 #size-cells = <0>;
1006 clocks = <&twi0_clk>;
1007 status = "disabled";
1008 };
1009
1010 i2c1: i2c@fff88000 {
1011 compatible = "atmel,at91sam9g10-i2c";
1012 reg = <0xfff88000 0x100>;
1013 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
1014 pinctrl-names = "default";
1015 pinctrl-0 = <&pinctrl_i2c1>;
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1018 clocks = <&twi1_clk>;
1019 status = "disabled";
1020 };
1021
1022 ssc0: ssc@fff9c000 {
1023 compatible = "atmel,at91sam9g45-ssc";
1024 reg = <0xfff9c000 0x4000>;
1025 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
1026 pinctrl-names = "default";
1027 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
1028 clocks = <&ssc0_clk>;
1029 clock-names = "pclk";
1030 status = "disabled";
1031 };
1032
1033 ssc1: ssc@fffa0000 {
1034 compatible = "atmel,at91sam9g45-ssc";
1035 reg = <0xfffa0000 0x4000>;
1036 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
1037 pinctrl-names = "default";
1038 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1039 clocks = <&ssc1_clk>;
1040 clock-names = "pclk";
1041 status = "disabled";
1042 };
1043
1044 adc0: adc@fffb0000 {
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1047 compatible = "atmel,at91sam9g45-adc";
1048 reg = <0xfffb0000 0x100>;
1049 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
1050 clocks = <&adc_clk>, <&adc_op_clk>;
1051 clock-names = "adc_clk", "adc_op_clk";
1052 atmel,adc-channels-used = <0xff>;
1053 atmel,adc-vref = <3300>;
1054 atmel,adc-startup-time = <40>;
1055 atmel,adc-res = <8 10>;
1056 atmel,adc-res-names = "lowres", "highres";
1057 atmel,adc-use-res = "highres";
1058
Wenyou Yangeb6f87c2017-04-18 13:49:36 +08001059 trigger0 {
Simon Glass6f967852016-05-05 07:28:12 -06001060 trigger-name = "external-rising";
1061 trigger-value = <0x1>;
1062 trigger-external;
1063 };
Wenyou Yangeb6f87c2017-04-18 13:49:36 +08001064 trigger1 {
Simon Glass6f967852016-05-05 07:28:12 -06001065 trigger-name = "external-falling";
1066 trigger-value = <0x2>;
1067 trigger-external;
1068 };
1069
Wenyou Yangeb6f87c2017-04-18 13:49:36 +08001070 trigger2 {
Simon Glass6f967852016-05-05 07:28:12 -06001071 trigger-name = "external-any";
1072 trigger-value = <0x3>;
1073 trigger-external;
1074 };
1075
Wenyou Yangeb6f87c2017-04-18 13:49:36 +08001076 trigger3 {
Simon Glass6f967852016-05-05 07:28:12 -06001077 trigger-name = "continuous";
1078 trigger-value = <0x6>;
1079 };
1080 };
1081
1082 isi@fffb4000 {
1083 compatible = "atmel,at91sam9g45-isi";
1084 reg = <0xfffb4000 0x4000>;
1085 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
1086 clocks = <&isi_clk>;
1087 clock-names = "isi_clk";
1088 status = "disabled";
1089 port {
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1092 };
1093 };
1094
1095 pwm0: pwm@fffb8000 {
1096 compatible = "atmel,at91sam9rl-pwm";
1097 reg = <0xfffb8000 0x300>;
1098 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
1099 #pwm-cells = <3>;
1100 clocks = <&pwm_clk>;
1101 status = "disabled";
1102 };
1103
1104 mmc0: mmc@fff80000 {
1105 compatible = "atmel,hsmci";
1106 reg = <0xfff80000 0x600>;
1107 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1108 pinctrl-names = "default";
1109 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
1110 dma-names = "rxtx";
1111 #address-cells = <1>;
1112 #size-cells = <0>;
1113 clocks = <&mci0_clk>;
1114 clock-names = "mci_clk";
1115 status = "disabled";
1116 };
1117
1118 mmc1: mmc@fffd0000 {
1119 compatible = "atmel,hsmci";
1120 reg = <0xfffd0000 0x600>;
1121 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
1122 pinctrl-names = "default";
1123 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
1124 dma-names = "rxtx";
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1127 clocks = <&mci1_clk>;
1128 clock-names = "mci_clk";
1129 status = "disabled";
1130 };
1131
1132 watchdog@fffffd40 {
1133 compatible = "atmel,at91sam9260-wdt";
1134 reg = <0xfffffd40 0x10>;
1135 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1136 clocks = <&clk32k>;
1137 atmel,watchdog-type = "hardware";
1138 atmel,reset-type = "all";
1139 atmel,dbg-halt;
1140 status = "disabled";
1141 };
1142
1143 spi0: spi@fffa4000 {
1144 #address-cells = <1>;
1145 #size-cells = <0>;
1146 compatible = "atmel,at91rm9200-spi";
1147 reg = <0xfffa4000 0x200>;
1148 interrupts = <14 4 3>;
1149 pinctrl-names = "default";
1150 pinctrl-0 = <&pinctrl_spi0>;
1151 clocks = <&spi0_clk>;
1152 clock-names = "spi_clk";
1153 status = "disabled";
1154 };
1155
1156 spi1: spi@fffa8000 {
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1159 compatible = "atmel,at91rm9200-spi";
1160 reg = <0xfffa8000 0x200>;
1161 interrupts = <15 4 3>;
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&pinctrl_spi1>;
1164 clocks = <&spi1_clk>;
1165 clock-names = "spi_clk";
1166 status = "disabled";
1167 };
1168
1169 usb2: gadget@fff78000 {
1170 #address-cells = <1>;
1171 #size-cells = <0>;
1172 compatible = "atmel,at91sam9g45-udc";
1173 reg = <0x00600000 0x80000
1174 0xfff78000 0x400>;
1175 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
1176 clocks = <&udphs_clk>, <&utmi>;
1177 clock-names = "pclk", "hclk";
1178 status = "disabled";
1179
Wenyou Yangeb6f87c2017-04-18 13:49:36 +08001180 ep@0 {
Simon Glass6f967852016-05-05 07:28:12 -06001181 reg = <0>;
1182 atmel,fifo-size = <64>;
1183 atmel,nb-banks = <1>;
1184 };
1185
Wenyou Yangeb6f87c2017-04-18 13:49:36 +08001186 ep@1 {
Simon Glass6f967852016-05-05 07:28:12 -06001187 reg = <1>;
1188 atmel,fifo-size = <1024>;
1189 atmel,nb-banks = <2>;
1190 atmel,can-dma;
1191 atmel,can-isoc;
1192 };
1193
Wenyou Yangeb6f87c2017-04-18 13:49:36 +08001194 ep@2 {
Simon Glass6f967852016-05-05 07:28:12 -06001195 reg = <2>;
1196 atmel,fifo-size = <1024>;
1197 atmel,nb-banks = <2>;
1198 atmel,can-dma;
1199 atmel,can-isoc;
1200 };
1201
Wenyou Yangeb6f87c2017-04-18 13:49:36 +08001202 ep@3 {
Simon Glass6f967852016-05-05 07:28:12 -06001203 reg = <3>;
1204 atmel,fifo-size = <1024>;
1205 atmel,nb-banks = <3>;
1206 atmel,can-dma;
1207 };
1208
Wenyou Yangeb6f87c2017-04-18 13:49:36 +08001209 ep@4 {
Simon Glass6f967852016-05-05 07:28:12 -06001210 reg = <4>;
1211 atmel,fifo-size = <1024>;
1212 atmel,nb-banks = <3>;
1213 atmel,can-dma;
1214 };
1215
Wenyou Yangeb6f87c2017-04-18 13:49:36 +08001216 ep@5 {
Simon Glass6f967852016-05-05 07:28:12 -06001217 reg = <5>;
1218 atmel,fifo-size = <1024>;
1219 atmel,nb-banks = <3>;
1220 atmel,can-dma;
1221 atmel,can-isoc;
1222 };
1223
Wenyou Yangeb6f87c2017-04-18 13:49:36 +08001224 ep@6 {
Simon Glass6f967852016-05-05 07:28:12 -06001225 reg = <6>;
1226 atmel,fifo-size = <1024>;
1227 atmel,nb-banks = <3>;
1228 atmel,can-dma;
1229 atmel,can-isoc;
1230 };
1231 };
1232
1233 sckc@fffffd50 {
1234 compatible = "atmel,at91sam9x5-sckc";
1235 reg = <0xfffffd50 0x4>;
1236
1237 slow_osc: slow_osc {
1238 compatible = "atmel,at91sam9x5-clk-slow-osc";
1239 #clock-cells = <0>;
1240 atmel,startup-time-usec = <1200000>;
1241 clocks = <&slow_xtal>;
1242 };
1243
1244 slow_rc_osc: slow_rc_osc {
1245 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1246 #clock-cells = <0>;
1247 atmel,startup-time-usec = <75>;
1248 clock-frequency = <32768>;
1249 clock-accuracy = <50000000>;
1250 };
1251
1252 clk32k: slck {
1253 compatible = "atmel,at91sam9x5-clk-slow";
1254 #clock-cells = <0>;
1255 clocks = <&slow_rc_osc &slow_osc>;
1256 };
1257 };
1258
1259 rtc@fffffd20 {
1260 compatible = "atmel,at91sam9260-rtt";
1261 reg = <0xfffffd20 0x10>;
1262 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1263 clocks = <&clk32k>;
1264 status = "disabled";
1265 };
1266
1267 rtc@fffffdb0 {
1268 compatible = "atmel,at91rm9200-rtc";
1269 reg = <0xfffffdb0 0x30>;
1270 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1271 clocks = <&clk32k>;
1272 status = "disabled";
1273 };
1274
1275 gpbr: syscon@fffffd60 {
1276 compatible = "atmel,at91sam9260-gpbr", "syscon";
1277 reg = <0xfffffd60 0x10>;
1278 status = "disabled";
1279 };
1280 };
1281
1282 fb0: fb@0x00500000 {
1283 compatible = "atmel,at91sam9g45-lcdc";
1284 reg = <0x00500000 0x1000>;
1285 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
1286 pinctrl-names = "default";
1287 pinctrl-0 = <&pinctrl_fb>;
1288 clocks = <&lcd_clk>, <&lcd_clk>;
1289 clock-names = "hclk", "lcdc_clk";
1290 status = "disabled";
1291 };
1292
1293 nand0: nand@40000000 {
1294 compatible = "atmel,at91rm9200-nand";
1295 #address-cells = <1>;
1296 #size-cells = <1>;
1297 reg = <0x40000000 0x10000000
1298 0xffffe200 0x200
1299 >;
1300 atmel,nand-addr-offset = <21>;
1301 atmel,nand-cmd-offset = <22>;
1302 atmel,nand-has-dma;
1303 pinctrl-names = "default";
1304 pinctrl-0 = <&pinctrl_nand>;
1305 gpios = <&pioC 8 GPIO_ACTIVE_HIGH
1306 &pioC 14 GPIO_ACTIVE_HIGH
1307 0
1308 >;
1309 status = "disabled";
1310 };
1311
1312 usb0: ohci@00700000 {
1313 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1314 reg = <0x00700000 0x100000>;
1315 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1316 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1317 clock-names = "ohci_clk", "hclk", "uhpck";
1318 status = "disabled";
1319 };
1320
1321 usb1: ehci@00800000 {
1322 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1323 reg = <0x00800000 0x100000>;
1324 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1325 clocks = <&utmi>, <&uhphs_clk>;
1326 clock-names = "usb_clk", "ehci_clk";
1327 status = "disabled";
1328 };
1329 };
1330
Wenyou Yangeb6f87c2017-04-18 13:49:36 +08001331 i2c-gpio-0 {
Simon Glass6f967852016-05-05 07:28:12 -06001332 compatible = "i2c-gpio";
1333 gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
1334 &pioA 21 GPIO_ACTIVE_HIGH /* scl */
1335 >;
1336 i2c-gpio,sda-open-drain;
1337 i2c-gpio,scl-open-drain;
1338 i2c-gpio,delay-us = <5>; /* ~100 kHz */
1339 #address-cells = <1>;
1340 #size-cells = <0>;
1341 status = "disabled";
1342 };
1343};