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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 82b896c1d0514c86fc959c41b493adadb84d6606 / . / arch / arm / dts / rk3588s-u-boot.dtsi
blob: 1e225d71efc2378b7ffce8f6ba34ab34cad0e504 [file] [log] [blame]
Jagan Teki2a8481e2023-01-30 20:27:46 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
4 */
5
6#include "rockchip-u-boot.dtsi"
7
8/ {
9 dmc {
10 compatible = "rockchip,rk3588-dmc";
Tom Rini82b896c2023-03-27 15:20:19 -0400[diff] [blame^]11 bootph-all;
Jagan Teki2a8481e2023-01-30 20:27:46 +0530[diff] [blame]12 status = "okay";
13 };
14
15 pmu1_grf: syscon@fd58a000 {
Tom Rini82b896c2023-03-27 15:20:19 -0400[diff] [blame^]16 bootph-all;
Jagan Teki2a8481e2023-01-30 20:27:46 +0530[diff] [blame]17 compatible = "rockchip,rk3588-pmu1-grf", "syscon";
18 reg = <0x0 0xfd58a000 0x0 0x2000>;
19 };
Jagan Teki95c86562023-01-30 20:27:47 +0530[diff] [blame]20
21 sdmmc: mmc@fe2c0000 {
22 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
23 reg = <0x0 0xfe2c0000 0x0 0x4000>;
24 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
25 clocks = <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>,
26 <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>;
27 clock-names = "ciu-drive", "ciu-sample", "biu", "ciu";
28 fifo-depth = <0x100>;
29 max-frequency = <200000000>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
32 status = "disabled";
33 };
Jonas Karlman3a539e02023-02-22 22:44:41 +0000[diff] [blame]34
35 otp: nvmem@fecc0000 {
36 compatible = "rockchip,rk3588-otp";
37 reg = <0x0 0xfecc0000 0x0 0x400>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 status = "okay";
41
42 cpu_id: id@7 {
43 reg = <0x07 0x10>;
44 };
45 };
Jagan Teki2a8481e2023-01-30 20:27:46 +0530[diff] [blame]46};
47
48&xin24m {
Tom Rini82b896c2023-03-27 15:20:19 -0400[diff] [blame^]49 bootph-all;
Jagan Teki2a8481e2023-01-30 20:27:46 +0530[diff] [blame]50 status = "okay";
51};
52
53&cru {
Tom Rini82b896c2023-03-27 15:20:19 -0400[diff] [blame^]54 bootph-pre-ram;
Jagan Teki2a8481e2023-01-30 20:27:46 +0530[diff] [blame]55 status = "okay";
56};
57
58&sys_grf {
Tom Rini82b896c2023-03-27 15:20:19 -0400[diff] [blame^]59 bootph-pre-ram;
Jagan Teki2a8481e2023-01-30 20:27:46 +0530[diff] [blame]60 status = "okay";
61};
62
63&uart2 {
64 clock-frequency = <24000000>;
Tom Rini82b896c2023-03-27 15:20:19 -0400[diff] [blame^]65 bootph-pre-ram;
Jagan Teki2a8481e2023-01-30 20:27:46 +0530[diff] [blame]66 status = "okay";
67};
68
69&ioc {
Tom Rini82b896c2023-03-27 15:20:19 -0400[diff] [blame^]70 bootph-pre-ram;
Jagan Teki2a8481e2023-01-30 20:27:46 +0530[diff] [blame]71};