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Dipen Dudhatd789b5f2011-01-20 16:29:35 +05301/*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05306 */
7
York Sun0b665132013-10-22 12:39:02 -07008#ifndef __FSL_IFC_H
9#define __FSL_IFC_H
Dipen Dudhatd789b5f2011-01-20 16:29:35 +053010
Mingkai Hu362ee042013-05-16 10:18:13 +080011#ifdef CONFIG_FSL_IFC
Dipen Dudhatd789b5f2011-01-20 16:29:35 +053012#include <config.h>
13#include <common.h>
14
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +053015
16#ifdef CONFIG_SYS_FSL_IFC_LE
17#define ifc_in32(a) in_le32(a)
18#define ifc_out32(a, v) out_le32(a, v)
19#define ifc_in16(a) in_le16(a)
20#elif defined(CONFIG_SYS_FSL_IFC_BE)
21#define ifc_in32(a) in_be32(a)
22#define ifc_out32(a, v) out_be32(a, v)
23#define ifc_in16(a) in_be16(a)
24#else
25#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined
26#endif
27
28
Dipen Dudhatd789b5f2011-01-20 16:29:35 +053029/*
30 * CSPR - Chip Select Property Register
31 */
32#define CSPR_BA 0xFFFF0000
33#define CSPR_BA_SHIFT 16
34#define CSPR_PORT_SIZE 0x00000180
35#define CSPR_PORT_SIZE_SHIFT 7
36/* Port Size 8 bit */
37#define CSPR_PORT_SIZE_8 0x00000080
38/* Port Size 16 bit */
39#define CSPR_PORT_SIZE_16 0x00000100
40/* Port Size 32 bit */
41#define CSPR_PORT_SIZE_32 0x00000180
42/* Write Protect */
43#define CSPR_WP 0x00000040
44#define CSPR_WP_SHIFT 6
45/* Machine Select */
46#define CSPR_MSEL 0x00000006
47#define CSPR_MSEL_SHIFT 1
48/* NOR */
49#define CSPR_MSEL_NOR 0x00000000
50/* NAND */
51#define CSPR_MSEL_NAND 0x00000002
52/* GPCM */
53#define CSPR_MSEL_GPCM 0x00000004
54/* Bank Valid */
55#define CSPR_V 0x00000001
56#define CSPR_V_SHIFT 0
57
58/* Convert an address into the right format for the CSPR Registers */
59#define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000)
60
61/*
62 * Address Mask Register
63 */
64#define IFC_AMASK_MASK 0xFFFF0000
65#define IFC_AMASK_SHIFT 16
66#define IFC_AMASK(n) (IFC_AMASK_MASK << \
67 (__ilog2(n) - IFC_AMASK_SHIFT))
68
69/*
70 * Chip Select Option Register IFC_NAND Machine
71 */
72/* Enable ECC Encoder */
73#define CSOR_NAND_ECC_ENC_EN 0x80000000
Dipen Dudhat52f90da2011-03-22 09:27:39 +053074#define CSOR_NAND_ECC_MODE_MASK 0x30000000
Dipen Dudhatd789b5f2011-01-20 16:29:35 +053075/* 4 bit correction per 520 Byte sector */
76#define CSOR_NAND_ECC_MODE_4 0x00000000
77/* 8 bit correction per 528 Byte sector */
78#define CSOR_NAND_ECC_MODE_8 0x10000000
79/* Enable ECC Decoder */
80#define CSOR_NAND_ECC_DEC_EN 0x04000000
81/* Row Address Length */
82#define CSOR_NAND_RAL_MASK 0x01800000
83#define CSOR_NAND_RAL_SHIFT 20
84#define CSOR_NAND_RAL_1 0x00000000
85#define CSOR_NAND_RAL_2 0x00800000
86#define CSOR_NAND_RAL_3 0x01000000
87#define CSOR_NAND_RAL_4 0x01800000
88/* Page Size 512b, 2k, 4k */
89#define CSOR_NAND_PGS_MASK 0x00180000
90#define CSOR_NAND_PGS_SHIFT 16
91#define CSOR_NAND_PGS_512 0x00000000
92#define CSOR_NAND_PGS_2K 0x00080000
93#define CSOR_NAND_PGS_4K 0x00100000
Prabhakar Kushwaha71220f82013-10-04 10:05:36 +053094#define CSOR_NAND_PGS_8K 0x00180000
Dipen Dudhatd789b5f2011-01-20 16:29:35 +053095/* Spare region Size */
96#define CSOR_NAND_SPRZ_MASK 0x0000E000
97#define CSOR_NAND_SPRZ_SHIFT 13
98#define CSOR_NAND_SPRZ_16 0x00000000
99#define CSOR_NAND_SPRZ_64 0x00002000
100#define CSOR_NAND_SPRZ_128 0x00004000
101#define CSOR_NAND_SPRZ_210 0x00006000
102#define CSOR_NAND_SPRZ_218 0x00008000
103#define CSOR_NAND_SPRZ_224 0x0000A000
Prabhakar Kushwaha71220f82013-10-04 10:05:36 +0530104#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530105/* Pages Per Block */
106#define CSOR_NAND_PB_MASK 0x00000700
107#define CSOR_NAND_PB_SHIFT 8
108#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
109/* Time for Read Enable High to Output High Impedance */
110#define CSOR_NAND_TRHZ_MASK 0x0000001C
111#define CSOR_NAND_TRHZ_SHIFT 2
112#define CSOR_NAND_TRHZ_20 0x00000000
113#define CSOR_NAND_TRHZ_40 0x00000004
114#define CSOR_NAND_TRHZ_60 0x00000008
115#define CSOR_NAND_TRHZ_80 0x0000000C
116#define CSOR_NAND_TRHZ_100 0x00000010
117/* Buffer control disable */
118#define CSOR_NAND_BCTLD 0x00000001
119
120/*
121 * Chip Select Option Register - NOR Flash Mode
122 */
123/* Enable Address shift Mode */
124#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
125/* Page Read Enable from NOR device */
126#define CSOR_NOR_PGRD_EN 0x10000000
127/* AVD Toggle Enable during Burst Program */
128#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
129/* Address Data Multiplexing Shift */
130#define CSOR_NOR_ADM_MASK 0x0003E000
131#define CSOR_NOR_ADM_SHIFT_SHIFT 13
132#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
133/* Type of the NOR device hooked */
134#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
135#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
136/* Time for Read Enable High to Output High Impedance */
137#define CSOR_NOR_TRHZ_MASK 0x0000001C
138#define CSOR_NOR_TRHZ_SHIFT 2
139#define CSOR_NOR_TRHZ_20 0x00000000
140#define CSOR_NOR_TRHZ_40 0x00000004
141#define CSOR_NOR_TRHZ_60 0x00000008
142#define CSOR_NOR_TRHZ_80 0x0000000C
143#define CSOR_NOR_TRHZ_100 0x00000010
144/* Buffer control disable */
145#define CSOR_NOR_BCTLD 0x00000001
146
147/*
148 * Chip Select Option Register - GPCM Mode
149 */
150/* GPCM Mode - Normal */
151#define CSOR_GPCM_GPMODE_NORMAL 0x00000000
152/* GPCM Mode - GenericASIC */
153#define CSOR_GPCM_GPMODE_ASIC 0x80000000
154/* Parity Mode odd/even */
155#define CSOR_GPCM_PARITY_EVEN 0x40000000
156/* Parity Checking enable/disable */
157#define CSOR_GPCM_PAR_EN 0x20000000
158/* GPCM Timeout Count */
159#define CSOR_GPCM_GPTO_MASK 0x0F000000
160#define CSOR_GPCM_GPTO_SHIFT 24
161#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
162/* GPCM External Access Termination mode for read access */
163#define CSOR_GPCM_RGETA_EXT 0x00080000
164/* GPCM External Access Termination mode for write access */
165#define CSOR_GPCM_WGETA_EXT 0x00040000
166/* Address Data Multiplexing Shift */
167#define CSOR_GPCM_ADM_MASK 0x0003E000
168#define CSOR_GPCM_ADM_SHIFT_SHIFT 13
169#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
170/* Generic ASIC Parity error indication delay */
171#define CSOR_GPCM_GAPERRD_MASK 0x00000180
172#define CSOR_GPCM_GAPERRD_SHIFT 7
173#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
174/* Time for Read Enable High to Output High Impedance */
175#define CSOR_GPCM_TRHZ_MASK 0x0000001C
176#define CSOR_GPCM_TRHZ_20 0x00000000
177#define CSOR_GPCM_TRHZ_40 0x00000004
178#define CSOR_GPCM_TRHZ_60 0x00000008
179#define CSOR_GPCM_TRHZ_80 0x0000000C
180#define CSOR_GPCM_TRHZ_100 0x00000010
181/* Buffer control disable */
182#define CSOR_GPCM_BCTLD 0x00000001
183
184/*
185 * Flash Timing Registers (FTIM0 - FTIM2_CSn)
186 */
187/*
188 * FTIM0 - NAND Flash Mode
189 */
190#define FTIM0_NAND 0x7EFF3F3F
191#define FTIM0_NAND_TCCST_SHIFT 25
192#define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT)
193#define FTIM0_NAND_TWP_SHIFT 16
194#define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT)
195#define FTIM0_NAND_TWCHT_SHIFT 8
196#define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT)
197#define FTIM0_NAND_TWH_SHIFT 0
198#define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT)
199/*
200 * FTIM1 - NAND Flash Mode
201 */
202#define FTIM1_NAND 0xFFFF3FFF
203#define FTIM1_NAND_TADLE_SHIFT 24
204#define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT)
205#define FTIM1_NAND_TWBE_SHIFT 16
206#define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT)
207#define FTIM1_NAND_TRR_SHIFT 8
208#define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT)
209#define FTIM1_NAND_TRP_SHIFT 0
210#define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT)
211/*
212 * FTIM2 - NAND Flash Mode
213 */
214#define FTIM2_NAND 0x1FE1F8FF
215#define FTIM2_NAND_TRAD_SHIFT 21
216#define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT)
217#define FTIM2_NAND_TREH_SHIFT 11
218#define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT)
219#define FTIM2_NAND_TWHRE_SHIFT 0
220#define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT)
221/*
222 * FTIM3 - NAND Flash Mode
223 */
224#define FTIM3_NAND 0xFF000000
225#define FTIM3_NAND_TWW_SHIFT 24
226#define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT)
227
228/*
229 * FTIM0 - NOR Flash Mode
230 */
231#define FTIM0_NOR 0xF03F3F3F
232#define FTIM0_NOR_TACSE_SHIFT 28
233#define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT)
234#define FTIM0_NOR_TEADC_SHIFT 16
235#define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT)
236#define FTIM0_NOR_TAVDS_SHIFT 8
237#define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT)
238#define FTIM0_NOR_TEAHC_SHIFT 0
239#define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT)
240/*
241 * FTIM1 - NOR Flash Mode
242 */
243#define FTIM1_NOR 0xFF003F3F
244#define FTIM1_NOR_TACO_SHIFT 24
245#define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT)
246#define FTIM1_NOR_TRAD_NOR_SHIFT 8
247#define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
248#define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
249#define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
250/*
251 * FTIM2 - NOR Flash Mode
252 */
253#define FTIM2_NOR 0x0F3CFCFF
254#define FTIM2_NOR_TCS_SHIFT 24
255#define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT)
256#define FTIM2_NOR_TCH_SHIFT 18
257#define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT)
258#define FTIM2_NOR_TWPH_SHIFT 10
259#define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT)
260#define FTIM2_NOR_TWP_SHIFT 0
261#define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT)
262
263/*
264 * FTIM0 - Normal GPCM Mode
265 */
266#define FTIM0_GPCM 0xF03F3F3F
267#define FTIM0_GPCM_TACSE_SHIFT 28
268#define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT)
269#define FTIM0_GPCM_TEADC_SHIFT 16
270#define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT)
271#define FTIM0_GPCM_TAVDS_SHIFT 8
272#define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT)
273#define FTIM0_GPCM_TEAHC_SHIFT 0
274#define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT)
275/*
276 * FTIM1 - Normal GPCM Mode
277 */
278#define FTIM1_GPCM 0xFF003F00
279#define FTIM1_GPCM_TACO_SHIFT 24
280#define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT)
281#define FTIM1_GPCM_TRAD_SHIFT 8
282#define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT)
283/*
284 * FTIM2 - Normal GPCM Mode
285 */
286#define FTIM2_GPCM 0x0F3C00FF
287#define FTIM2_GPCM_TCS_SHIFT 24
288#define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT)
289#define FTIM2_GPCM_TCH_SHIFT 18
290#define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT)
291#define FTIM2_GPCM_TWP_SHIFT 0
292#define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT)
293
294/*
295 * Ready Busy Status Register (RB_STAT)
296 */
297/* CSn is READY */
298#define IFC_RB_STAT_READY_CS0 0x80000000
299#define IFC_RB_STAT_READY_CS1 0x40000000
300#define IFC_RB_STAT_READY_CS2 0x20000000
301#define IFC_RB_STAT_READY_CS3 0x10000000
302
303/*
304 * General Control Register (GCR)
305 */
306#define IFC_GCR_MASK 0x8000F800
307/* reset all IFC hardware */
308#define IFC_GCR_SOFT_RST_ALL 0x80000000
309/* Turnaroud Time of external buffer */
310#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
311#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
312
313/*
314 * Common Event and Error Status Register (CM_EVTER_STAT)
315 */
316/* Chip select error */
317#define IFC_CM_EVTER_STAT_CSER 0x80000000
318
319/*
320 * Common Event and Error Enable Register (CM_EVTER_EN)
321 */
322/* Chip select error checking enable */
323#define IFC_CM_EVTER_EN_CSEREN 0x80000000
324
325/*
326 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
327 */
328/* Chip select error interrupt enable */
329#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
330
331/*
332 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
333 */
334/* transaction type of error Read/Write */
335#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
336#define IFC_CM_ERATTR0_ERAID 0x0FF00000
337#define IFC_CM_ERATTR0_ESRCID 0x0000FF00
338
339/*
340 * Clock Control Register (CCR)
341 */
342#define IFC_CCR_MASK 0x0F0F8800
343/* Clock division ratio */
344#define IFC_CCR_CLK_DIV_MASK 0x0F000000
345#define IFC_CCR_CLK_DIV_SHIFT 24
346#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
347/* IFC Clock Delay */
348#define IFC_CCR_CLK_DLY_MASK 0x000F0000
349#define IFC_CCR_CLK_DLY_SHIFT 16
350#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
351/* Invert IFC clock before sending out */
352#define IFC_CCR_INV_CLK_EN 0x00008000
353/* Fedback IFC Clock */
354#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
355
356/*
357 * Clock Status Register (CSR)
358 */
359/* Clk is stable */
360#define IFC_CSR_CLK_STAT_STABLE 0x80000000
361
362/*
363 * IFC_NAND Machine Specific Registers
364 */
365/*
366 * NAND Configuration Register (NCFGR)
367 */
368/* Auto Boot Mode */
369#define IFC_NAND_NCFGR_BOOT 0x80000000
370/* Addressing Mode-ROW0+n/COL0 */
371#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
372/* Addressing Mode-ROW0+n/COL0+n */
373#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
374/* Number of loop iterations of FIR sequences for multi page operations */
375#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
376#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
377#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
378/* Number of wait cycles */
379#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
380#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
381
382/*
383 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
384 */
385/* General purpose FCM flash command bytes CMD0-CMD7 */
386#define IFC_NAND_FCR0_CMD0 0xFF000000
387#define IFC_NAND_FCR0_CMD0_SHIFT 24
388#define IFC_NAND_FCR0_CMD1 0x00FF0000
389#define IFC_NAND_FCR0_CMD1_SHIFT 16
390#define IFC_NAND_FCR0_CMD2 0x0000FF00
391#define IFC_NAND_FCR0_CMD2_SHIFT 8
392#define IFC_NAND_FCR0_CMD3 0x000000FF
393#define IFC_NAND_FCR0_CMD3_SHIFT 0
394#define IFC_NAND_FCR1_CMD4 0xFF000000
395#define IFC_NAND_FCR1_CMD4_SHIFT 24
396#define IFC_NAND_FCR1_CMD5 0x00FF0000
397#define IFC_NAND_FCR1_CMD5_SHIFT 16
398#define IFC_NAND_FCR1_CMD6 0x0000FF00
399#define IFC_NAND_FCR1_CMD6_SHIFT 8
400#define IFC_NAND_FCR1_CMD7 0x000000FF
401#define IFC_NAND_FCR1_CMD7_SHIFT 0
402
403/*
404 * Flash ROW and COL Address Register (ROWn, COLn)
405 */
406/* Main/spare region locator */
407#define IFC_NAND_COL_MS 0x80000000
408/* Column Address */
409#define IFC_NAND_COL_CA_MASK 0x00000FFF
410
411/*
412 * NAND Flash Byte Count Register (NAND_BC)
413 */
414/* Byte Count for read/Write */
415#define IFC_NAND_BC 0x000001FF
416
417/*
418 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
419 */
420/* NAND Machine specific opcodes OP0-OP14*/
421#define IFC_NAND_FIR0_OP0 0xFC000000
422#define IFC_NAND_FIR0_OP0_SHIFT 26
423#define IFC_NAND_FIR0_OP1 0x03F00000
424#define IFC_NAND_FIR0_OP1_SHIFT 20
425#define IFC_NAND_FIR0_OP2 0x000FC000
426#define IFC_NAND_FIR0_OP2_SHIFT 14
427#define IFC_NAND_FIR0_OP3 0x00003F00
428#define IFC_NAND_FIR0_OP3_SHIFT 8
429#define IFC_NAND_FIR0_OP4 0x000000FC
430#define IFC_NAND_FIR0_OP4_SHIFT 2
431#define IFC_NAND_FIR1_OP5 0xFC000000
432#define IFC_NAND_FIR1_OP5_SHIFT 26
433#define IFC_NAND_FIR1_OP6 0x03F00000
434#define IFC_NAND_FIR1_OP6_SHIFT 20
435#define IFC_NAND_FIR1_OP7 0x000FC000
436#define IFC_NAND_FIR1_OP7_SHIFT 14
437#define IFC_NAND_FIR1_OP8 0x00003F00
438#define IFC_NAND_FIR1_OP8_SHIFT 8
439#define IFC_NAND_FIR1_OP9 0x000000FC
440#define IFC_NAND_FIR1_OP9_SHIFT 2
441#define IFC_NAND_FIR2_OP10 0xFC000000
442#define IFC_NAND_FIR2_OP10_SHIFT 26
443#define IFC_NAND_FIR2_OP11 0x03F00000
444#define IFC_NAND_FIR2_OP11_SHIFT 20
445#define IFC_NAND_FIR2_OP12 0x000FC000
446#define IFC_NAND_FIR2_OP12_SHIFT 14
447#define IFC_NAND_FIR2_OP13 0x00003F00
448#define IFC_NAND_FIR2_OP13_SHIFT 8
449#define IFC_NAND_FIR2_OP14 0x000000FC
450#define IFC_NAND_FIR2_OP14_SHIFT 2
451
452/*
453 * Instruction opcodes to be programmed
454 * in FIR registers- 6bits
455 */
456enum ifc_nand_fir_opcodes {
457 IFC_FIR_OP_NOP,
458 IFC_FIR_OP_CA0,
459 IFC_FIR_OP_CA1,
460 IFC_FIR_OP_CA2,
461 IFC_FIR_OP_CA3,
462 IFC_FIR_OP_RA0,
463 IFC_FIR_OP_RA1,
464 IFC_FIR_OP_RA2,
465 IFC_FIR_OP_RA3,
466 IFC_FIR_OP_CMD0,
467 IFC_FIR_OP_CMD1,
468 IFC_FIR_OP_CMD2,
469 IFC_FIR_OP_CMD3,
470 IFC_FIR_OP_CMD4,
471 IFC_FIR_OP_CMD5,
472 IFC_FIR_OP_CMD6,
473 IFC_FIR_OP_CMD7,
474 IFC_FIR_OP_CW0,
475 IFC_FIR_OP_CW1,
476 IFC_FIR_OP_CW2,
477 IFC_FIR_OP_CW3,
478 IFC_FIR_OP_CW4,
479 IFC_FIR_OP_CW5,
480 IFC_FIR_OP_CW6,
481 IFC_FIR_OP_CW7,
482 IFC_FIR_OP_WBCD,
483 IFC_FIR_OP_RBCD,
484 IFC_FIR_OP_BTRD,
485 IFC_FIR_OP_RDSTAT,
486 IFC_FIR_OP_NWAIT,
487 IFC_FIR_OP_WFR,
488 IFC_FIR_OP_SBRD,
489 IFC_FIR_OP_UA,
490 IFC_FIR_OP_RB,
491};
492
493/*
494 * NAND Chip Select Register (NAND_CSEL)
495 */
496#define IFC_NAND_CSEL 0x0C000000
497#define IFC_NAND_CSEL_SHIFT 26
498#define IFC_NAND_CSEL_CS0 0x00000000
499#define IFC_NAND_CSEL_CS1 0x04000000
500#define IFC_NAND_CSEL_CS2 0x08000000
501#define IFC_NAND_CSEL_CS3 0x0C000000
502
503/*
504 * NAND Operation Sequence Start (NANDSEQ_STRT)
505 */
506/* NAND Flash Operation Start */
507#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
508/* Automatic Erase */
509#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
510/* Automatic Program */
511#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
512/* Automatic Copyback */
513#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
514/* Automatic Read Operation */
515#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
516/* Automatic Status Read */
517#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
518
519/*
520 * NAND Event and Error Status Register (NAND_EVTER_STAT)
521 */
522/* Operation Complete */
523#define IFC_NAND_EVTER_STAT_OPC 0x80000000
524/* Flash Timeout Error */
525#define IFC_NAND_EVTER_STAT_FTOER 0x08000000
526/* Write Protect Error */
527#define IFC_NAND_EVTER_STAT_WPER 0x04000000
528/* ECC Error */
529#define IFC_NAND_EVTER_STAT_ECCER 0x02000000
530/* RCW Load Done */
531#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
532/* Boot Loadr Done */
533#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
534/* Bad Block Indicator search select */
535#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
536
537/*
538 * NAND Flash Page Read Completion Event Status Register
539 * (PGRDCMPL_EVT_STAT)
540 */
541#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
542/* Small Page 0-15 Done */
543#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
544/* Large Page(2K) 0-3 Done */
545#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
546/* Large Page(4K) 0-1 Done */
547#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
548
549/*
550 * NAND Event and Error Enable Register (NAND_EVTER_EN)
551 */
552/* Operation complete event enable */
553#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
554/* Page read complete event enable */
555#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
556/* Flash Timeout error enable */
557#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
558/* Write Protect error enable */
559#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
560/* ECC error logging enable */
561#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
562
563/*
564 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
565 */
566/* Enable interrupt for operation complete */
567#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
568/* Enable interrupt for Page read complete */
569#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
570/* Enable interrupt for Flash timeout error */
571#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
572/* Enable interrupt for Write protect error */
573#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
574/* Enable interrupt for ECC error*/
575#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
576
577/*
578 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
579 */
580#define IFC_NAND_ERATTR0_MASK 0x0C080000
581/* Error on CS0-3 for NAND */
582#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
583#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
584#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
585#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
586/* Transaction type of error Read/Write */
587#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
588
589/*
590 * NAND Flash Status Register (NAND_FSR)
591 */
592/* First byte of data read from read status op */
593#define IFC_NAND_NFSR_RS0 0xFF000000
594/* Second byte of data read from read status op */
595#define IFC_NAND_NFSR_RS1 0x00FF0000
596
597/*
598 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
599 */
600/* Number of ECC errors on sector n (n = 0-15) */
601#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
602#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
603#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
604#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
605#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
606#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
607#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
608#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
609#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
610#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
611#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
612#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
613#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
614#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
615#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
616#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
617#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
618#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
619#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
620#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
621#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
622#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
623#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
624#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
625#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
626#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
627#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
628#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
629#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
630#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
631#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
632#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
633
634/*
635 * NAND Control Register (NANDCR)
636 */
637#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
638#define IFC_NAND_NCR_FTOCNT_SHIFT 25
639#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
640
641/*
642 * NAND_AUTOBOOT_TRGR
643 */
644/* Trigger RCW load */
645#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
646/* Trigget Auto Boot */
647#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
648
649/*
650 * NAND_MDR
651 */
652/* 1st read data byte when opcode SBRD */
653#define IFC_NAND_MDR_RDATA0 0xFF000000
654/* 2nd read data byte when opcode SBRD */
655#define IFC_NAND_MDR_RDATA1 0x00FF0000
656
657/*
658 * NOR Machine Specific Registers
659 */
660/*
661 * NOR Event and Error Status Register (NOR_EVTER_STAT)
662 */
663/* NOR Command Sequence Operation Complete */
664#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
665/* Write Protect Error */
666#define IFC_NOR_EVTER_STAT_WPER 0x04000000
667/* Command Sequence Timeout Error */
668#define IFC_NOR_EVTER_STAT_STOER 0x01000000
669
670/*
671 * NOR Event and Error Enable Register (NOR_EVTER_EN)
672 */
673/* NOR Command Seq complete event enable */
674#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
675/* Write Protect Error Checking Enable */
676#define IFC_NOR_EVTER_EN_WPEREN 0x04000000
677/* Timeout Error Enable */
678#define IFC_NOR_EVTER_EN_STOEREN 0x01000000
679
680/*
681 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
682 */
683/* Enable interrupt for OPC complete */
684#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
685/* Enable interrupt for write protect error */
686#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
687/* Enable interrupt for timeout error */
688#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
689
690/*
691 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
692 */
693/* Source ID for error transaction */
694#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
695/* AXI ID for error transation */
696#define IFC_NOR_ERATTR0_ERAID 0x000FF000
697/* Chip select corresponds to NOR error */
698#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
699#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
700#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
701#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
702/* Type of transaction read/write */
703#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
704
705/*
706 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
707 */
708#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
709#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
710
711/*
712 * NOR Control Register (NORCR)
713 */
714#define IFC_NORCR_MASK 0x0F0F0000
715/* No. of Address/Data Phase */
716#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
717#define IFC_NORCR_NUM_PHASE_SHIFT 24
718#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
719/* Sequence Timeout Count */
720#define IFC_NORCR_STOCNT_MASK 0x000F0000
721#define IFC_NORCR_STOCNT_SHIFT 16
722#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
723
724/*
725 * GPCM Machine specific registers
726 */
727/*
728 * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
729 */
730/* Timeout error */
731#define IFC_GPCM_EVTER_STAT_TOER 0x04000000
732/* Parity error */
733#define IFC_GPCM_EVTER_STAT_PER 0x01000000
734
735/*
736 * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
737 */
738/* Timeout error enable */
739#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
740/* Parity error enable */
741#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
742
743/*
744 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
745 */
746/* Enable Interrupt for timeout error */
747#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
748/* Enable Interrupt for Parity error */
749#define IFC_GPCM_EEIER_PERIR_EN 0x01000000
750
751/*
752 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
753 */
754/* Source ID for error transaction */
755#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
756/* AXI ID for error transaction */
757#define IFC_GPCM_ERATTR0_ERAID 0x000FF000
758/* Chip select corresponds to GPCM error */
759#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
760#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
761#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
762#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
763/* Type of transaction read/Write */
764#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
765
766/*
767 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
768 */
769/* On which beat of address/data parity error is observed */
770#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
771/* Parity Error on byte */
772#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
773/* Parity Error reported in addr or data phase */
774#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
775
776/*
777 * GPCM Status Register (GPCM_STAT)
778 */
779#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
780
781
782#ifndef __ASSEMBLY__
783#include <asm/io.h>
784
785extern void print_ifc_regs(void);
786extern void init_early_memctl_regs(void);
787
788#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
789
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +0530790#define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
791#define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
792#define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
793#define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
794#define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
795#define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530796
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +0530797#define set_ifc_cspr_ext(i, v) \
798 (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
799#define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
800#define set_ifc_csor_ext(i, v) \
801 (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
802#define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
803#define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530804#define set_ifc_ftim(i, j, v) \
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +0530805 (ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530806
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530807enum ifc_chip_sel {
808 IFC_CS0,
809 IFC_CS1,
810 IFC_CS2,
811 IFC_CS3,
Mingkai Hu362ee042013-05-16 10:18:13 +0800812 IFC_CS4,
813 IFC_CS5,
814 IFC_CS6,
815 IFC_CS7,
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530816};
817
818enum ifc_ftims {
819 IFC_FTIM0,
820 IFC_FTIM1,
821 IFC_FTIM2,
822 IFC_FTIM3,
823};
824
825/*
826 * IFC Controller NAND Machine registers
827 */
828struct fsl_ifc_nand {
829 u32 ncfgr;
830 u32 res1[0x4];
831 u32 nand_fcr0;
832 u32 nand_fcr1;
833 u32 res2[0x8];
834 u32 row0;
835 u32 res3;
836 u32 col0;
837 u32 res4;
838 u32 row1;
839 u32 res5;
840 u32 col1;
841 u32 res6;
842 u32 row2;
843 u32 res7;
844 u32 col2;
845 u32 res8;
846 u32 row3;
847 u32 res9;
848 u32 col3;
849 u32 res10[0x24];
850 u32 nand_fbcr;
851 u32 res11;
852 u32 nand_fir0;
853 u32 nand_fir1;
854 u32 nand_fir2;
855 u32 res12[0x10];
856 u32 nand_csel;
857 u32 res13;
858 u32 nandseq_strt;
859 u32 res14;
860 u32 nand_evter_stat;
861 u32 res15;
862 u32 pgrdcmpl_evt_stat;
863 u32 res16[0x2];
864 u32 nand_evter_en;
865 u32 res17[0x2];
866 u32 nand_evter_intr_en;
867 u32 res18[0x2];
868 u32 nand_erattr0;
869 u32 nand_erattr1;
870 u32 res19[0x10];
871 u32 nand_fsr;
872 u32 res20;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530873 u32 nand_eccstat[4];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530874 u32 res21[0x20];
875 u32 nanndcr;
876 u32 res22[0x2];
877 u32 nand_autoboot_trgr;
878 u32 res23;
879 u32 nand_mdr;
880 u32 res24[0x5C];
881};
882
883/*
884 * IFC controller NOR Machine registers
885 */
886struct fsl_ifc_nor {
887 u32 nor_evter_stat;
888 u32 res1[0x2];
889 u32 nor_evter_en;
890 u32 res2[0x2];
891 u32 nor_evter_intr_en;
892 u32 res3[0x2];
893 u32 nor_erattr0;
894 u32 nor_erattr1;
895 u32 nor_erattr2;
896 u32 res4[0x4];
897 u32 norcr;
898 u32 res5[0xEF];
899};
900
901/*
902 * IFC controller GPCM Machine registers
903 */
904struct fsl_ifc_gpcm {
905 u32 gpcm_evter_stat;
906 u32 res1[0x2];
907 u32 gpcm_evter_en;
908 u32 res2[0x2];
909 u32 gpcm_evter_intr_en;
910 u32 res3[0x2];
911 u32 gpcm_erattr0;
912 u32 gpcm_erattr1;
913 u32 gpcm_erattr2;
914 u32 gpcm_stat;
915 u32 res4[0x1F3];
916};
917
Mingkai Hu362ee042013-05-16 10:18:13 +0800918#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
919#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
920#define IFC_CSPR_REG_LEN 148
921#define IFC_AMASK_REG_LEN 144
922#define IFC_CSOR_REG_LEN 144
923#define IFC_FTIM_REG_LEN 576
924
925#define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \
926 CONFIG_SYS_FSL_IFC_BANK_COUNT
927#define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \
928 CONFIG_SYS_FSL_IFC_BANK_COUNT
929#define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \
930 CONFIG_SYS_FSL_IFC_BANK_COUNT
931#define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \
932 CONFIG_SYS_FSL_IFC_BANK_COUNT
933#else
934#error IFC BANK count not vaild
935#endif
936#else
937#error IFC BANK count not defined
938#endif
939
940struct fsl_ifc_cspr {
941 u32 cspr_ext;
942 u32 cspr;
943 u32 res;
944};
945
946struct fsl_ifc_amask {
947 u32 amask;
948 u32 res[0x2];
949};
950
951struct fsl_ifc_csor {
952 u32 csor;
953 u32 csor_ext;
954 u32 res;
955};
956
957struct fsl_ifc_ftim {
958 u32 ftim[4];
959 u32 res[0x8];
960};
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530961
962/*
963 * IFC Controller Registers
964 */
965struct fsl_ifc {
966 u32 ifc_rev;
Kumar Galaffdf8892012-08-17 08:20:25 +0000967 u32 res1[0x2];
Mingkai Hu362ee042013-05-16 10:18:13 +0800968 struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
969 u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
970 struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
971 u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
972 struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
973 u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
974 struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
975 u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530976 u32 rb_stat;
Mingkai Hu362ee042013-05-16 10:18:13 +0800977 u32 res6[0x2];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530978 u32 ifc_gcr;
Mingkai Hu362ee042013-05-16 10:18:13 +0800979 u32 res7[0x2];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530980 u32 cm_evter_stat;
Mingkai Hu362ee042013-05-16 10:18:13 +0800981 u32 res8[0x2];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530982 u32 cm_evter_en;
Mingkai Hu362ee042013-05-16 10:18:13 +0800983 u32 res9[0x2];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530984 u32 cm_evter_intr_en;
Mingkai Hu362ee042013-05-16 10:18:13 +0800985 u32 res10[0x2];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530986 u32 cm_erattr0;
987 u32 cm_erattr1;
Mingkai Hu362ee042013-05-16 10:18:13 +0800988 u32 res11[0x2];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530989 u32 ifc_ccr;
990 u32 ifc_csr;
Mingkai Hu362ee042013-05-16 10:18:13 +0800991 u32 res12[0x2EB];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530992 struct fsl_ifc_nand ifc_nand;
993 struct fsl_ifc_nor ifc_nor;
994 struct fsl_ifc_gpcm ifc_gpcm;
995};
996
Poonam Aggrwal42aee642011-06-30 03:00:28 -0500997#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
998#undef CSPR_MSEL_NOR
999#define CSPR_MSEL_NOR CSPR_MSEL_GPCM
1000#endif
Mingkai Hu362ee042013-05-16 10:18:13 +08001001#endif /* CONFIG_FSL_IFC */
Poonam Aggrwal42aee642011-06-30 03:00:28 -05001002
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05301003#endif /* __ASSEMBLY__ */
York Sun0b665132013-10-22 12:39:02 -07001004#endif /* __FSL_IFC_H */