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Chris Packham3c265bb2019-02-16 11:48:58 +13001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
Phil Sutteraefb8f42015-12-25 14:41:25 +01002/*
3 * Device Tree file for Synology DS414
4 *
5 * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
6 *
Phil Sutteraefb8f42015-12-25 14:41:25 +01007 * Note: this Device Tree assumes that the bootloader has remapped the
8 * internal registers to 0xf1000000 (instead of the old 0xd0000000).
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
10 * bootloaders provided by Marvell. It is used in recent versions of
11 * DSM software provided by Synology. Nonetheless, some earlier boards
12 * were delivered with an older version of u-boot that left internal
13 * registers mapped at 0xd0000000. If you have such a device you will
14 * not be able to directly boot a kernel based on this Device Tree. In
15 * that case, the preferred solution is to update your bootloader (e.g.
16 * by upgrading to latest version of DSM, or building a new one and
17 * installing it from u-boot prompt) or adjust the Devive Tree
18 * (s/0xf1000000/0xd0000000/ in 'ranges' below).
19 */
20
21/dts-v1/;
22
23#include <dt-bindings/input/input.h>
24#include <dt-bindings/gpio/gpio.h>
25#include "armada-xp-mv78230.dtsi"
26
27/ {
28 model = "Synology DS414";
29 compatible = "synology,ds414", "marvell,armadaxp-mv78230",
30 "marvell,armadaxp", "marvell,armada-370-xp";
31
32 chosen {
33 bootargs = "console=ttyS0,115200 earlyprintk";
34 stdout-path = &uart0;
35 };
36
37 aliases {
38 spi0 = &spi0;
39 };
40
Chris Packham3c265bb2019-02-16 11:48:58 +130041 memory@0 {
Phil Sutteraefb8f42015-12-25 14:41:25 +010042 device_type = "memory";
43 reg = <0 0x00000000 0 0x40000000>; /* 1GB */
44 };
45
46 soc {
47 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
Chris Packham3c265bb2019-02-16 11:48:58 +130048 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
49 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
50 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
Phil Sutteraefb8f42015-12-25 14:41:25 +010051
52 internal-regs {
53
54 /* RTC is provided by Seiko S-35390A below */
55 rtc@10300 {
56 status = "disabled";
57 };
58
Phil Sutteraefb8f42015-12-25 14:41:25 +010059 i2c@11000 {
60 clock-frequency = <400000>;
61 status = "okay";
62
63 s35390a: s35390a@30 {
64 compatible = "sii,s35390a";
65 reg = <0x30>;
66 };
67 };
68
69 /* Connected to a header on device's PCB. This
70 * provides the main console for the device.
71 *
72 * Warning: the device may not boot with a 3.3V
73 * USB-serial converter connected when the power
74 * button is pressed. The converter needs to be
75 * connected a few seconds after pressing the
76 * power button. This is possibly due to UART0_TXD
77 * pin being sampled at reset (bit 0 of SAR).
78 */
79 serial@12000 {
80 status = "okay";
Phil Sutteraefb8f42015-12-25 14:41:25 +010081 };
82
83 /* Connected to a Microchip PIC16F883 for power control */
84 serial@12100 {
85 status = "okay";
86 };
87
88 poweroff@12100 {
89 compatible = "synology,power-off";
90 reg = <0x12100 0x100>;
91 clocks = <&coreclk 0>;
92 };
93
94 /* Front USB 2.0 port */
95 usb@50000 {
96 status = "okay";
97 };
98
Phil Sutteraefb8f42015-12-25 14:41:25 +010099 ethernet@70000 {
100 status = "okay";
101 pinctrl-0 = <&ge0_rgmii_pins>;
102 pinctrl-names = "default";
103 phy = <&phy1>;
104 phy-mode = "rgmii-id";
105 };
106
107 ethernet@74000 {
108 pinctrl-0 = <&ge1_rgmii_pins>;
109 pinctrl-names = "default";
110 status = "okay";
111 phy = <&phy0>;
112 phy-mode = "rgmii-id";
113 };
114 };
115 };
116
117 regulators {
118 compatible = "simple-bus";
119 #address-cells = <1>;
120 #size-cells = <0>;
121 pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin
122 &sata3_pwr_pin &sata4_pwr_pin>;
123 pinctrl-names = "default";
124
Chris Packham3c265bb2019-02-16 11:48:58 +1300125 sata1_regulator: sata1-regulator@1 {
Phil Sutteraefb8f42015-12-25 14:41:25 +0100126 compatible = "regulator-fixed";
127 reg = <1>;
128 regulator-name = "SATA1 Power";
129 regulator-min-microvolt = <5000000>;
130 regulator-max-microvolt = <5000000>;
131 startup-delay-us = <2000000>;
132 enable-active-high;
133 regulator-always-on;
134 regulator-boot-on;
135 gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
136 };
137
Chris Packham3c265bb2019-02-16 11:48:58 +1300138 sata2_regulator: sata2-regulator@2 {
Phil Sutteraefb8f42015-12-25 14:41:25 +0100139 compatible = "regulator-fixed";
140 reg = <2>;
141 regulator-name = "SATA2 Power";
142 regulator-min-microvolt = <5000000>;
143 regulator-max-microvolt = <5000000>;
144 startup-delay-us = <4000000>;
145 enable-active-high;
146 regulator-always-on;
147 regulator-boot-on;
148 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
149 };
150
Chris Packham3c265bb2019-02-16 11:48:58 +1300151 sata3_regulator: sata3-regulator@3 {
Phil Sutteraefb8f42015-12-25 14:41:25 +0100152 compatible = "regulator-fixed";
153 reg = <3>;
154 regulator-name = "SATA3 Power";
155 regulator-min-microvolt = <5000000>;
156 regulator-max-microvolt = <5000000>;
157 startup-delay-us = <6000000>;
158 enable-active-high;
159 regulator-always-on;
160 regulator-boot-on;
161 gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
162 };
163
Chris Packham3c265bb2019-02-16 11:48:58 +1300164 sata4_regulator: sata4-regulator@4 {
Phil Sutteraefb8f42015-12-25 14:41:25 +0100165 compatible = "regulator-fixed";
166 reg = <4>;
167 regulator-name = "SATA4 Power";
168 regulator-min-microvolt = <5000000>;
169 regulator-max-microvolt = <5000000>;
170 startup-delay-us = <8000000>;
171 enable-active-high;
172 regulator-always-on;
173 regulator-boot-on;
174 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
175 };
176 };
177};
178
Chris Packham3c265bb2019-02-16 11:48:58 +1300179&pciec {
180 status = "okay";
181
182 /*
183 * Connected to Marvell 88SX7042 SATA-II controller
184 * handling the four disks.
185 */
186 pcie@1,0 {
187 /* Port 0, Lane 0 */
188 status = "okay";
Pali Rohár94c30f92021-12-21 12:20:19 +0100189 num-lanes = <4>;
Chris Packham3c265bb2019-02-16 11:48:58 +1300190 };
191
192 /*
193 * Connected to EtronTech EJ168A XHCI controller
194 * providing the two rear USB 3.0 ports.
195 */
196 pcie@5,0 {
197 /* Port 1, Lane 0 */
198 status = "okay";
199 };
200};
201
202
203&mdio {
204 phy0: ethernet-phy@0 { /* Marvell 88E1512 */
205 reg = <0>;
206 };
207
208 phy1: ethernet-phy@1 { /* Marvell 88E1512 */
209 reg = <1>;
210 };
211};
212
Phil Sutteraefb8f42015-12-25 14:41:25 +0100213&pinctrl {
214 sata1_pwr_pin: sata1-pwr-pin {
215 marvell,pins = "mpp42";
216 marvell,function = "gpio";
217 };
218
219 sata2_pwr_pin: sata2-pwr-pin {
220 marvell,pins = "mpp44";
221 marvell,function = "gpio";
222 };
223
224 sata3_pwr_pin: sata3-pwr-pin {
225 marvell,pins = "mpp45";
226 marvell,function = "gpio";
227 };
228
229 sata4_pwr_pin: sata4-pwr-pin {
230 marvell,pins = "mpp46";
231 marvell,function = "gpio";
232 };
233
234 sata1_pres_pin: sata1-pres-pin {
235 marvell,pins = "mpp34";
236 marvell,function = "gpio";
237 };
238
239 sata2_pres_pin: sata2-pres-pin {
240 marvell,pins = "mpp35";
241 marvell,function = "gpio";
242 };
243
244 sata3_pres_pin: sata3-pres-pin {
245 marvell,pins = "mpp40";
246 marvell,function = "gpio";
247 };
248
249 sata4_pres_pin: sata4-pres-pin {
250 marvell,pins = "mpp41";
251 marvell,function = "gpio";
252 };
253
254 syno_id_bit0_pin: syno-id-bit0-pin {
255 marvell,pins = "mpp26";
256 marvell,function = "gpio";
257 };
258
259 syno_id_bit1_pin: syno-id-bit1-pin {
260 marvell,pins = "mpp28";
261 marvell,function = "gpio";
262 };
263
264 syno_id_bit2_pin: syno-id-bit2-pin {
265 marvell,pins = "mpp29";
266 marvell,function = "gpio";
267 };
268
269 fan1_alarm_pin: fan1-alarm-pin {
270 marvell,pins = "mpp33";
271 marvell,function = "gpio";
272 };
273
274 fan2_alarm_pin: fan2-alarm-pin {
275 marvell,pins = "mpp32";
276 marvell,function = "gpio";
277 };
278};
Chris Packham3c265bb2019-02-16 11:48:58 +1300279
280&spi0 {
281 status = "okay";
282
283 spi-flash@0 {
284 #address-cells = <1>;
285 #size-cells = <1>;
286 compatible = "micron,n25q064", "jedec,spi-nor";
287 reg = <0>; /* Chip select 0 */
288 spi-max-frequency = <20000000>;
289
290 /*
291 * Warning!
292 *
293 * Synology u-boot uses its compiled-in environment
294 * and it seems Synology did not care to change u-boot
295 * default configuration in order to allow saving a
296 * modified environment at a sensible location. So,
297 * if you do a 'saveenv' under u-boot, your modified
298 * environment will be saved at 1MB after the start
299 * of the flash, i.e. in the middle of the uImage.
300 * For that reason, it is strongly advised not to
301 * change the default environment, unless you know
302 * what you are doing.
303 */
304 partition@0 { /* u-boot */
305 label = "RedBoot";
306 reg = <0x00000000 0x000d0000>; /* 832KB */
307 };
308
309 partition@c0000 { /* uImage */
310 label = "zImage";
311 reg = <0x000d0000 0x002d0000>; /* 2880KB */
312 };
313
314 partition@3a0000 { /* uInitramfs */
315 label = "rd.gz";
316 reg = <0x003a0000 0x00430000>; /* 4250KB */
317 };
318
319 partition@7d0000 { /* MAC address and serial number */
320 label = "vendor";
321 reg = <0x007d0000 0x00010000>; /* 64KB */
322 };
323
324 partition@7e0000 {
325 label = "RedBoot config";
326 reg = <0x007e0000 0x00010000>; /* 64KB */
327 };
328
329 partition@7f0000 {
330 label = "FIS directory";
331 reg = <0x007f0000 0x00010000>; /* 64KB */
332 };
333 };
334};