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Weijie Gao6bd888b2020-04-21 09:28:49 +02001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 *
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 */
7
8#ifndef __CONFIG_MT7628_H
9#define __CONFIG_MT7628_H
10
Tom Riniaa6e94d2022-11-16 13:10:37 -050011#define CFG_SYS_SDRAM_BASE 0x80000000
Weijie Gao6bd888b2020-04-21 09:28:49 +020012
Tom Rini65cc0e22022-11-16 13:10:41 -050013#define CFG_SYS_INIT_SP_OFFSET 0x80000
Weijie Gao6bd888b2020-04-21 09:28:49 +020014
Weijie Gao6bd888b2020-04-21 09:28:49 +020015/* Serial SPL */
Simon Glass2a736062021-08-08 12:20:12 -060016#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
Tom Rini91092132022-11-16 13:10:28 -050017#define CFG_SYS_NS16550_CLK 40000000
18#define CFG_SYS_NS16550_COM1 0xb0000c00
Weijie Gao6bd888b2020-04-21 09:28:49 +020019#endif
20
21/* Serial common */
Tom Rini65cc0e22022-11-16 13:10:41 -050022#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
Weijie Gao6bd888b2020-04-21 09:28:49 +020023 230400, 460800, 921600 }
24
25/* SPL */
Weijie Gao6bd888b2020-04-21 09:28:49 +020026
Tom Rini65cc0e22022-11-16 13:10:41 -050027#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
Weijie Gao6bd888b2020-04-21 09:28:49 +020028
29/* Dummy value */
Tom Rini65cc0e22022-11-16 13:10:41 -050030#define CFG_SYS_UBOOT_BASE 0
Weijie Gao6bd888b2020-04-21 09:28:49 +020031
32#endif /* __CONFIG_MT7628_H */