blob: 90a62ea47e57341e155324996a9ddc0d4fa8d3a0 [file] [log] [blame]
Stefan Roese0d974d52007-03-24 15:57:09 +01001/*
Stefan Roesec813f1f2008-03-11 16:53:00 +01002 * (C) Copyright 2007-2008
Stefan Roese0d974d52007-03-24 15:57:09 +01003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese0d974d52007-03-24 15:57:09 +01006 */
7
Stefan Roeseaee747f2007-11-15 14:23:55 +01008#ifndef __ASM_PPC_GPIO_H
9#define __ASM_PPC_GPIO_H
10
Matthias Fuchsda799f62009-07-20 12:15:38 +020011#include <asm/types.h>
12
Stefan Roese0d974d52007-03-24 15:57:09 +010013/* 4xx PPC's have 2 GPIO controllers */
14#if defined(CONFIG_405EZ) || \
15 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
Stefan Roesec813f1f2008-03-11 16:53:00 +010016 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
17 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roese0d974d52007-03-24 15:57:09 +010018#define GPIO_GROUP_MAX 2
19#else
20#define GPIO_GROUP_MAX 1
21#endif
22
Matthias Fuchsda799f62009-07-20 12:15:38 +020023/* GPIO controller */
24struct ppc4xx_gpio {
25 u32 or; /* Output Control */
26 u32 tcr; /* Tri-State Control */
27 u32 osl; /* Output Select 16..31 */
28 u32 osh; /* Output Select 0..15 */
29 u32 tsl; /* Tri-State Select 16..31 */
30 u32 tsh; /* Tri-State Select 0..15 */
31 u32 odr; /* Open Drain */
32 u32 ir; /* Input */
33 u32 rr1; /* Receive Register 1 */
34 u32 rr2; /* Receive Register 2 */
35 u32 rr3; /* Receive Register 3 */
36 u32 reserved;
37 u32 is1l; /* Input Select 1 16..31 */
38 u32 is1h; /* Input Select 1 0..15 */
39 u32 is2l; /* Input Select 2 16..31 */
40 u32 is2h; /* Input Select 2 0..15 */
41 u32 is3l; /* Input Select 3 16..31 */
42 u32 is3h; /* Input Select 3 0..15 */
43};
44
Stefan Roeseaee747f2007-11-15 14:23:55 +010045/* Offsets */
46#define GPIOx_OR 0x00 /* GPIO Output Register */
47#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
48#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
49#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
50#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
51#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
52#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
53#define GPIOx_IR 0x1C /* GPIO Input Register */
54#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
55#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
56#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
57#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
58#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
59#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
60#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
61#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
62#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
63
64#define GPIO_OR(x) (x+GPIOx_OR) /* GPIO Output Register */
65#define GPIO_TCR(x) (x+GPIOx_TCR) /* GPIO Three-State Control Register */
66#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Select Register High or Low */
67#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
68#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
69#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
70#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
71
72#define GPIO0 0
73#define GPIO1 1
74
Stefan Roese0d974d52007-03-24 15:57:09 +010075#define GPIO_MAX 32
76#define GPIO_ALT1_SEL 0x40000000
77#define GPIO_ALT2_SEL 0x80000000
78#define GPIO_ALT3_SEL 0xc0000000
79#define GPIO_IN_SEL 0x40000000
80#define GPIO_MASK 0xc0000000
81
82#define GPIO_VAL(gpio) (0x80000000 >> (gpio))
83
84#ifndef __ASSEMBLY__
85typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
86typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
87typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;
88
89typedef struct {
Stefan Roese85f73732007-06-15 07:39:43 +020090 unsigned long add; /* gpio core base address */
91 gpio_driver_t in_out; /* Driver Setting */
92 gpio_select_t alt_nb; /* Selected Alternate */
93 gpio_out_t out_val;/* Default Output Value */
Stefan Roese0d974d52007-03-24 15:57:09 +010094} gpio_param_s;
95#endif
96
97void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
98void gpio_write_bit(int pin, int val);
Stefan Roese85f73732007-06-15 07:39:43 +020099int gpio_read_out_bit(int pin);
Lawrence R. Johnson5ab884b2008-01-03 18:54:00 -0500100int gpio_read_in_bit(int pin);
Stefan Roese0d974d52007-03-24 15:57:09 +0100101void gpio_set_chip_configuration(void);
Stefan Roeseaee747f2007-11-15 14:23:55 +0100102
103#endif /* __ASM_PPC_GPIO_H */