blob: 099bdecc8c28a79c5f09905736342eac72fe9920 [file] [log] [blame]
Joe Hammanc646bba2007-08-09 15:11:03 -05001/*
2 * Copyright 2007 Wind River Systems <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 * Joe Hamman <joe.hamman@embeddedspecialties.com>
5 *
6 * Copyright 2006 Freescale Semiconductor.
7 *
8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
30 * SBC8641D board configuration file
31 *
32 * Make sure you change the MAC address and other network params first,
33 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/* High Level Configuration Options */
40#define CONFIG_MPC86xx 1 /* MPC86xx */
41#define CONFIG_MPC8641 1 /* MPC8641 specific */
42#define CONFIG_SBC8641D 1 /* SBC8641D board specific */
Kumar Gala7649a592009-03-31 23:02:38 -050043#define CONFIG_MP 1 /* support multiple processors */
Joe Hammanc646bba2007-08-09 15:11:03 -050044#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
45
Wolfgang Denk2ae18242010-10-06 09:05:45 +020046#define CONFIG_SYS_TEXT_BASE 0xfff00000
47
Joe Hammanc646bba2007-08-09 15:11:03 -050048#ifdef RUN_DIAG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_DIAG_ADDR 0xff800000
Joe Hammanc646bba2007-08-09 15:11:03 -050050#endif
51
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
Joe Hammanc646bba2007-08-09 15:11:03 -050053
Becky Bruce1266df82008-11-03 15:44:01 -060054/*
55 * virtual address to be used for temporary mappings. There
56 * should be 128k free at this VA.
57 */
58#define CONFIG_SYS_SCRATCH_VA 0xe8000000
59
Kumar Gala7cee1df2011-01-04 17:48:51 -060060#define CONFIG_SYS_SRIO
61#define CONFIG_SRIO1 /* SRIO port 1 */
62
Joe Hammancca34962007-08-11 06:54:58 -050063#define CONFIG_PCI 1 /* Enable PCIE */
Kumar Gala46f3e382010-07-09 00:02:34 -050064#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
65#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
Joe Hammancca34962007-08-11 06:54:58 -050066#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Becky Bruce713d8182008-01-23 16:31:03 -060067#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Joe Hammanc646bba2007-08-09 15:11:03 -050068
Wolfgang Denk53677ef2008-05-20 16:00:29 +020069#define CONFIG_TSEC_ENET /* tsec ethernet support */
Joe Hammanc646bba2007-08-09 15:11:03 -050070#define CONFIG_ENV_OVERWRITE
71
Peter Tyser4bbfd3e2010-10-07 22:32:48 -050072#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Becky Bruce23f935c2008-08-04 14:01:16 -050073#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
74
Joe Hammanc646bba2007-08-09 15:11:03 -050075#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
Wolfgang Denk53677ef2008-05-20 16:00:29 +020076#undef CONFIG_DDR_ECC /* only for ECC DDR module */
Joe Hammanc646bba2007-08-09 15:11:03 -050077#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
78#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
79#define CONFIG_NUM_DDR_CONTROLLERS 2
80#define CACHE_LINE_INTERLEAVING 0x20000000
81#define PAGE_INTERLEAVING 0x21000000
82#define BANK_INTERLEAVING 0x22000000
83#define SUPER_BANK_INTERLEAVING 0x23000000
84
85
86#define CONFIG_ALTIVEC 1
87
88/*
89 * L2CR setup -- make sure this is right for your board!
90 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_L2
Joe Hammanc646bba2007-08-09 15:11:03 -050092#define L2_INIT 0
93#define L2_ENABLE (L2CR_L2E)
94
95#ifndef CONFIG_SYS_CLK_FREQ
96#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
97#endif
98
99#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
102#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
103#define CONFIG_SYS_MEMTEST_END 0x00400000
Joe Hammanc646bba2007-08-09 15:11:03 -0500104
105/*
106 * Base addresses -- Note these are effective addresses where the
107 * actual resources get mapped (not physical addresses)
108 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
110#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
111#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Joe Hammanc646bba2007-08-09 15:11:03 -0500112
Jon Loeligerf6987382008-11-20 14:02:56 -0600113#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
114#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
Kumar Galaad19e7a2009-08-05 07:59:35 -0500115#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
Jon Loeligerf6987382008-11-20 14:02:56 -0600116
Joe Hammanc646bba2007-08-09 15:11:03 -0500117/*
118 * DDR Setup
119 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
121#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
122#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
123#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
Becky Bruce1266df82008-11-03 15:44:01 -0600124#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
Joe Hammanc646bba2007-08-09 15:11:03 -0500125#define CONFIG_VERY_BIG_RAM
126
Kumar Gala9bd4e592008-08-26 15:01:37 -0500127#define CONFIG_NUM_DDR_CONTROLLERS 2
128#define CONFIG_DIMM_SLOTS_PER_CTLR 2
129#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
130
Joe Hammanc646bba2007-08-09 15:11:03 -0500131#if defined(CONFIG_SPD_EEPROM)
132 /*
133 * Determine DDR configuration from I2C interface.
134 */
135 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
136 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
137 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
138 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
139
140#else
141 /*
142 * Manually set up DDR1 & DDR2 parameters
143 */
144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
Joe Hammanc646bba2007-08-09 15:11:03 -0500146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
148 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
149 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
150 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
151 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
152 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
153 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
154 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
155 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
156 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
157 #define CONFIG_SYS_DDR_TIMING_1 0x38377322
158 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7
159 #define CONFIG_SYS_DDR_CFG_1A 0x43008008
160 #define CONFIG_SYS_DDR_CFG_2 0x24401000
161 #define CONFIG_SYS_DDR_MODE_1 0x23c00542
162 #define CONFIG_SYS_DDR_MODE_2 0x00000000
163 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000
164 #define CONFIG_SYS_DDR_INTERVAL 0x05080100
165 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000
166 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
167 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008
Joe Hammanc646bba2007-08-09 15:11:03 -0500168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
170 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
171 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
172 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
173 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
174 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
175 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
176 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
177 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
178 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802
179 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322
180 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
181 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008
182 #define CONFIG_SYS_DDR2_CFG_2 0x24401000
183 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542
184 #define CONFIG_SYS_DDR2_MODE_2 0x00000000
185 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
186 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100
187 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
188 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
189 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
Joe Hammanc646bba2007-08-09 15:11:03 -0500190
191
192#endif
193
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200194/* #define CONFIG_ID_EEPROM 1
Joe Hammanc646bba2007-08-09 15:11:03 -0500195#define ID_EEPROM_ADDR 0x57 */
196
197/*
198 * The SBC8641D contains 16MB flash space at ff000000.
199 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
Joe Hammanc646bba2007-08-09 15:11:03 -0500201
202/* Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
204#define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */
Joe Hammanc646bba2007-08-09 15:11:03 -0500205
206/* 64KB EEPROM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */
208#define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */
Joe Hammanc646bba2007-08-09 15:11:03 -0500209
210/* EPLD - User switches, board id, LEDs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */
212#define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */
Joe Hammanc646bba2007-08-09 15:11:03 -0500213
214/* Local bus SDRAM 128MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */
216#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
217#define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */
218#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
Joe Hammanc646bba2007-08-09 15:11:03 -0500219
220/* Disk on Chip (DOC) 128MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */
222#define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
Joe Hammanc646bba2007-08-09 15:11:03 -0500223
224/* LCD */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */
226#define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
Joe Hammanc646bba2007-08-09 15:11:03 -0500227
228/* Control logic & misc peripherals */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */
230#define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
Joe Hammanc646bba2007-08-09 15:11:03 -0500231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
233#define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */
Joe Hammanc646bba2007-08-09 15:11:03 -0500234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#undef CONFIG_SYS_FLASH_CHECKSUM
236#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
237#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200238#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Becky Brucebf9a8c32008-11-05 14:55:35 -0600239#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
Joe Hammanc646bba2007-08-09 15:11:03 -0500240
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200241#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_FLASH_CFI
243#define CONFIG_SYS_WRITE_SWAPPED_DATA
244#define CONFIG_SYS_FLASH_EMPTY_INFO
245#define CONFIG_SYS_FLASH_PROTECTION
Joe Hammanc646bba2007-08-09 15:11:03 -0500246
247#undef CONFIG_CLOCKS_IN_MHZ
248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_INIT_RAM_LOCK 1
250#ifndef CONFIG_SYS_INIT_RAM_LOCK
251#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
Joe Hammanc646bba2007-08-09 15:11:03 -0500252#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
Joe Hammanc646bba2007-08-09 15:11:03 -0500254#endif
Wolfgang Denk553f0982010-10-26 13:32:32 +0200255#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Joe Hammanc646bba2007-08-09 15:11:03 -0500256
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200257#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Joe Hammanc646bba2007-08-09 15:11:03 -0500259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
261#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Joe Hammanc646bba2007-08-09 15:11:03 -0500262
263/* Serial Port */
264#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_NS16550
266#define CONFIG_SYS_NS16550_SERIAL
267#define CONFIG_SYS_NS16550_REG_SIZE 1
268#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Joe Hammanc646bba2007-08-09 15:11:03 -0500269
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hammanc646bba2007-08-09 15:11:03 -0500271 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
274#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Joe Hammanc646bba2007-08-09 15:11:03 -0500275
276/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_HUSH_PARSER
278#ifdef CONFIG_SYS_HUSH_PARSER
279#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Joe Hammanc646bba2007-08-09 15:11:03 -0500280#endif
281
282/*
283 * Pass open firmware flat tree to kernel
284 */
Jon Loeliger13f54332008-02-18 14:01:56 -0600285#define CONFIG_OF_LIBFDT 1
286#define CONFIG_OF_BOARD_SETUP 1
287#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Joe Hammanc646bba2007-08-09 15:11:03 -0500288
Joe Hammanc646bba2007-08-09 15:11:03 -0500289/*
290 * I2C
291 */
292#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
293#define CONFIG_HARD_I2C /* I2C with hardware support*/
294#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
296#define CONFIG_SYS_I2C_SLAVE 0x7F
297#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
298#define CONFIG_SYS_I2C_OFFSET 0x3100
Joe Hammanc646bba2007-08-09 15:11:03 -0500299
300/*
301 * RapidIO MMU
302 */
Kumar Gala7cee1df2011-01-04 17:48:51 -0600303#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */
304#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
305#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
Joe Hammanc646bba2007-08-09 15:11:03 -0500306
307/*
308 * General PCI
309 * Addresses are mapped 1-1.
310 */
Kumar Gala46f3e382010-07-09 00:02:34 -0500311#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
312#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
313#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
314#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
315#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
316#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
317#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
318#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
Joe Hammanc646bba2007-08-09 15:11:03 -0500319
Kumar Gala46f3e382010-07-09 00:02:34 -0500320#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
321#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
322#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
323#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
324#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
325#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
326#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
327#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */
Joe Hammanc646bba2007-08-09 15:11:03 -0500328
329#if defined(CONFIG_PCI)
330
331#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
332
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
Joe Hammanc646bba2007-08-09 15:11:03 -0500334
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200335#define CONFIG_PCI_PNP /* do pci plug-and-play */
Joe Hammanc646bba2007-08-09 15:11:03 -0500336
337#undef CONFIG_EEPRO100
338#undef CONFIG_TULIP
339
340#if !defined(CONFIG_PCI_PNP)
341 #define PCI_ENET0_IOADDR 0xe0000000
342 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200343 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
Joe Hammanc646bba2007-08-09 15:11:03 -0500344#endif
345
346#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
347
348#define CONFIG_DOS_PARTITION
349#undef CONFIG_SCSI_AHCI
350
351#ifdef CONFIG_SCSI_AHCI
352#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
354#define CONFIG_SYS_SCSI_MAX_LUN 1
355#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
356#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Joe Hammanc646bba2007-08-09 15:11:03 -0500357#endif
358
359#endif /* CONFIG_PCI */
360
361#if defined(CONFIG_TSEC_ENET)
362
Joe Hammanc646bba2007-08-09 15:11:03 -0500363/* #define CONFIG_MII 1 */ /* MII PHY management */
364
365#define CONFIG_TSEC1 1
366#define CONFIG_TSEC1_NAME "eTSEC1"
367#define CONFIG_TSEC2 1
368#define CONFIG_TSEC2_NAME "eTSEC2"
369#define CONFIG_TSEC3 1
370#define CONFIG_TSEC3_NAME "eTSEC3"
371#define CONFIG_TSEC4 1
372#define CONFIG_TSEC4_NAME "eTSEC4"
373
374#define TSEC1_PHY_ADDR 0x1F
375#define TSEC2_PHY_ADDR 0x00
376#define TSEC3_PHY_ADDR 0x01
377#define TSEC4_PHY_ADDR 0x02
378#define TSEC1_PHYIDX 0
379#define TSEC2_PHYIDX 0
380#define TSEC3_PHYIDX 0
381#define TSEC4_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500382#define TSEC1_FLAGS TSEC_GIGABIT
383#define TSEC2_FLAGS TSEC_GIGABIT
384#define TSEC3_FLAGS TSEC_GIGABIT
385#define TSEC4_FLAGS TSEC_GIGABIT
Joe Hammanc646bba2007-08-09 15:11:03 -0500386
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
Joe Hammanc646bba2007-08-09 15:11:03 -0500388
389#define CONFIG_ETHPRIME "eTSEC1"
390
391#endif /* CONFIG_TSEC_ENET */
392
393/*
394 * BAT0 2G Cacheable, non-guarded
395 * 0x0000_0000 2G DDR
396 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
398#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
399#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
400#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
Joe Hammanc646bba2007-08-09 15:11:03 -0500401
402/*
403 * BAT1 1G Cache-inhibited, guarded
404 * 0x8000_0000 512M PCI-Express 1 Memory
405 * 0xa000_0000 512M PCI-Express 2 Memory
406 * Changed it for operating from 0xd0000000
407 */
Kumar Gala46f3e382010-07-09 00:02:34 -0500408#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
Joe Hammanc646bba2007-08-09 15:11:03 -0500409 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500410#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
411#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
Joe Hammanc646bba2007-08-09 15:11:03 -0500413
414/*
415 * BAT2 512M Cache-inhibited, guarded
416 * 0xc000_0000 512M RapidIO Memory
417 */
Kumar Gala7cee1df2011-01-04 17:48:51 -0600418#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
Joe Hammanc646bba2007-08-09 15:11:03 -0500419 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Kumar Gala7cee1df2011-01-04 17:48:51 -0600420#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
421#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
Joe Hammanc646bba2007-08-09 15:11:03 -0500423
424/*
425 * BAT3 4M Cache-inhibited, guarded
426 * 0xf800_0000 4M CCSR
427 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
Joe Hammanc646bba2007-08-09 15:11:03 -0500429 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
431#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
432#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
Joe Hammanc646bba2007-08-09 15:11:03 -0500433
Jon Loeligerf6987382008-11-20 14:02:56 -0600434#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
435#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
436 | BATL_PP_RW | BATL_CACHEINHIBIT \
437 | BATL_GUARDEDSTORAGE)
438#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
439 | BATU_BL_1M | BATU_VS | BATU_VP)
440#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
441 | BATL_PP_RW | BATL_CACHEINHIBIT)
442#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
443#endif
444
Joe Hammanc646bba2007-08-09 15:11:03 -0500445/*
446 * BAT4 32M Cache-inhibited, guarded
447 * 0xe200_0000 16M PCI-Express 1 I/O
448 * 0xe300_0000 16M PCI-Express 2 I/0
449 * Note that this is at 0xe0000000
450 */
Kumar Gala46f3e382010-07-09 00:02:34 -0500451#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
Joe Hammanc646bba2007-08-09 15:11:03 -0500452 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500453#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
454#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
Joe Hammanc646bba2007-08-09 15:11:03 -0500456
457/*
458 * BAT5 128K Cacheable, non-guarded
459 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
460 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
462#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
463#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
464#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
Joe Hammanc646bba2007-08-09 15:11:03 -0500465
466/*
467 * BAT6 32M Cache-inhibited, guarded
468 * 0xfe00_0000 32M FLASH
469 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
Joe Hammanc646bba2007-08-09 15:11:03 -0500471 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
473#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
474#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
Joe Hammanc646bba2007-08-09 15:11:03 -0500475
Becky Brucebf9a8c32008-11-05 14:55:35 -0600476/* Map the last 1M of flash where we're running from reset */
477#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
478 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200479#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
Becky Brucebf9a8c32008-11-05 14:55:35 -0600480#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
481 | BATL_MEMCOHERENCE)
482#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
483
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484#define CONFIG_SYS_DBAT7L 0x00000000
485#define CONFIG_SYS_DBAT7U 0x00000000
486#define CONFIG_SYS_IBAT7L 0x00000000
487#define CONFIG_SYS_IBAT7U 0x00000000
Joe Hammanc646bba2007-08-09 15:11:03 -0500488
489/*
490 * Environment
491 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200492#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200494#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
495#define CONFIG_ENV_SIZE 0x2000
Joe Hammanc646bba2007-08-09 15:11:03 -0500496
497#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200498#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Joe Hammanc646bba2007-08-09 15:11:03 -0500499
500#include <config_cmd_default.h>
501 #define CONFIG_CMD_PING
502 #define CONFIG_CMD_I2C
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600503 #define CONFIG_CMD_REGINFO
Joe Hammanc646bba2007-08-09 15:11:03 -0500504
505#if defined(CONFIG_PCI)
506 #define CONFIG_CMD_PCI
507#endif
508
509#undef CONFIG_WATCHDOG /* watchdog disabled */
510
511/*
512 * Miscellaneous configurable options
513 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#define CONFIG_SYS_LONGHELP /* undef to save memory */
515#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
516#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Joe Hammanc646bba2007-08-09 15:11:03 -0500517
Jon Loeliger30b52df2007-08-15 11:55:35 -0500518#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200519 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Joe Hammanc646bba2007-08-09 15:11:03 -0500520#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Joe Hammanc646bba2007-08-09 15:11:03 -0500522#endif
523
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200524#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
525#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
526#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
527#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Joe Hammanc646bba2007-08-09 15:11:03 -0500528
529/*
530 * For booting Linux, the board info and command line data
531 * have to be in the first 8 MB of memory, since this is
532 * the maximum mapped by the Linux kernel during initialization.
533 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200534#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Joe Hammanc646bba2007-08-09 15:11:03 -0500535
536/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200537#define CONFIG_SYS_DCACHE_SIZE 32768
538#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeliger30b52df2007-08-15 11:55:35 -0500539#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200540#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
Joe Hammanc646bba2007-08-09 15:11:03 -0500541#endif
542
Jon Loeliger30b52df2007-08-15 11:55:35 -0500543#if defined(CONFIG_CMD_KGDB)
Joe Hammanc646bba2007-08-09 15:11:03 -0500544#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
545#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
546#endif
547
548/*
549 * Environment Configuration
550 */
551
552/* The mac addresses for all ethernet interface */
553#if defined(CONFIG_TSEC_ENET)
554#define CONFIG_ETHADDR 02:E0:0C:00:00:01
555#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
556#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD
557#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD
558#endif
559
Andy Fleming10327dc2007-08-16 16:35:02 -0500560#define CONFIG_HAS_ETH0 1
Joe Hammanc646bba2007-08-09 15:11:03 -0500561#define CONFIG_HAS_ETH1 1
562#define CONFIG_HAS_ETH2 1
563#define CONFIG_HAS_ETH3 1
564
565#define CONFIG_IPADDR 192.168.0.50
566
567#define CONFIG_HOSTNAME sbc8641d
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000568#define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000569#define CONFIG_BOOTFILE "uImage"
Joe Hammanc646bba2007-08-09 15:11:03 -0500570
571#define CONFIG_SERVERIP 192.168.0.2
572#define CONFIG_GATEWAYIP 192.168.0.1
573#define CONFIG_NETMASK 255.255.255.0
574
575/* default location for tftp and bootm */
576#define CONFIG_LOADADDR 1000000
577
578#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
579#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
580
581#define CONFIG_BAUDRATE 115200
582
583#define CONFIG_EXTRA_ENV_SETTINGS \
584 "netdev=eth0\0" \
585 "consoledev=ttyS0\0" \
586 "ramdiskaddr=2000000\0" \
587 "ramdiskfile=uRamdisk\0" \
588 "dtbaddr=400000\0" \
589 "dtbfile=sbc8641d.dtb\0" \
590 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
591 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
592 "maxcpus=1"
593
594#define CONFIG_NFSBOOTCOMMAND \
595 "setenv bootargs root=/dev/nfs rw " \
596 "nfsroot=$serverip:$rootpath " \
597 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
598 "console=$consoledev,$baudrate $othbootargs;" \
599 "tftp $loadaddr $bootfile;" \
600 "tftp $dtbaddr $dtbfile;" \
601 "bootm $loadaddr - $dtbaddr"
602
603#define CONFIG_RAMBOOTCOMMAND \
604 "setenv bootargs root=/dev/ram rw " \
605 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
606 "console=$consoledev,$baudrate $othbootargs;" \
607 "tftp $ramdiskaddr $ramdiskfile;" \
608 "tftp $loadaddr $bootfile;" \
609 "tftp $dtbaddr $dtbfile;" \
610 "bootm $loadaddr $ramdiskaddr $dtbaddr"
611
612#define CONFIG_FLASHBOOTCOMMAND \
613 "setenv bootargs root=/dev/ram rw " \
614 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
615 "console=$consoledev,$baudrate $othbootargs;" \
616 "bootm ffd00000 ffb00000 ffa00000"
617
618#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
619
620#endif /* __CONFIG_H */