| Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> |
| 3 | * |
| Tom Rini | 0b17998 | 2013-07-24 09:34:30 -0400 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0 |
| Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| Gabor Juhos | ac12984 | 2013-05-22 03:57:41 +0000 | [diff] [blame] | 7 | #include <config.h> |
| 8 | #include <gt64120.h> |
| 9 | |
| 10 | #include <asm/addrspace.h> |
| Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 11 | #include <asm/regdef.h> |
| Gabor Juhos | ac12984 | 2013-05-22 03:57:41 +0000 | [diff] [blame] | 12 | #include <asm/malta.h> |
| 13 | |
| 14 | #ifdef CONFIG_SYS_BIG_ENDIAN |
| 15 | #define CPU_TO_GT32(_x) ((_x)) |
| 16 | #else |
| 17 | #define CPU_TO_GT32(_x) ( \ |
| 18 | (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ |
| 19 | (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) |
| 20 | #endif |
| Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 21 | |
| 22 | .text |
| 23 | .set noreorder |
| 24 | .set mips32 |
| 25 | |
| 26 | .globl lowlevel_init |
| 27 | lowlevel_init: |
| 28 | |
| Gabor Juhos | ac12984 | 2013-05-22 03:57:41 +0000 | [diff] [blame] | 29 | /* |
| 30 | * Load BAR registers of GT64120 as done by YAMON |
| 31 | * |
| 32 | * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com> |
| 33 | * to the barebox mailing list. |
| 34 | * The subject of the original patch: |
| 35 | * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' |
| 36 | * URL: |
| 37 | * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html |
| 38 | * |
| 39 | * based on write_bootloader() in qemu.git/hw/mips_malta.c |
| 40 | * see GT64120 manual and qemu.git/hw/gt64xxx.c for details |
| 41 | */ |
| 42 | |
| 43 | /* move GT64120 registers from 0x14000000 to 0x1be00000 */ |
| 44 | li t1, KSEG1ADDR(GT_DEF_BASE) |
| 45 | li t0, CPU_TO_GT32(0xdf000000) |
| 46 | sw t0, GT_ISD_OFS(t1) |
| 47 | |
| 48 | /* setup MEM-to-PCI0 mapping */ |
| 49 | li t1, KSEG1ADDR(MALTA_GT_BASE) |
| 50 | |
| 51 | /* setup PCI0 io window to 0x18000000-0x181fffff */ |
| 52 | li t0, CPU_TO_GT32(0xc0000000) |
| 53 | sw t0, GT_PCI0IOLD_OFS(t1) |
| 54 | li t0, CPU_TO_GT32(0x40000000) |
| 55 | sw t0, GT_PCI0IOHD_OFS(t1) |
| 56 | |
| 57 | /* setup PCI0 mem windows */ |
| 58 | li t0, CPU_TO_GT32(0x80000000) |
| 59 | sw t0, GT_PCI0M0LD_OFS(t1) |
| 60 | li t0, CPU_TO_GT32(0x3f000000) |
| 61 | sw t0, GT_PCI0M0HD_OFS(t1) |
| 62 | |
| 63 | li t0, CPU_TO_GT32(0xc1000000) |
| 64 | sw t0, GT_PCI0M1LD_OFS(t1) |
| 65 | li t0, CPU_TO_GT32(0x5e000000) |
| 66 | sw t0, GT_PCI0M1HD_OFS(t1) |
| 67 | |
| Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 68 | jr ra |
| 69 | nop |