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stroese13fdf8a2003-09-12 08:55:18 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405EP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_DP405 1 /* ...on a DP405 board */
stroese13fdf8a2003-09-12 08:55:18 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroese13fdf8a2003-09-12 08:55:18 +000042
stroesea20b27a2004-12-16 18:05:42 +000043#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */
stroese13fdf8a2003-09-12 08:55:18 +000044
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
47
48#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000049#undef CONFIG_BOOTCOMMAND
stroese13fdf8a2003-09-12 08:55:18 +000050
stroesea20b27a2004-12-16 18:05:42 +000051#define CONFIG_PREBOOT /* enable preboot variable */
52
stroese13fdf8a2003-09-12 08:55:18 +000053#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
54
55#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000056#define CONFIG_PHY_ADDR 0 /* PHY address */
stroese13fdf8a2003-09-12 08:55:18 +000057
58#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
59 CFG_CMD_BSP | \
60 CFG_CMD_DHCP | \
61 CFG_CMD_IRQ | \
62 CFG_CMD_ELF | \
63 CFG_CMD_DATE | \
64 CFG_CMD_I2C | \
wdenkc837dcb2004-01-20 23:12:12 +000065 CFG_CMD_EEPROM )
stroese13fdf8a2003-09-12 08:55:18 +000066
67/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
68#include <cmd_confdefs.h>
69
wdenkc837dcb2004-01-20 23:12:12 +000070#undef CONFIG_WATCHDOG /* watchdog disabled */
stroese13fdf8a2003-09-12 08:55:18 +000071
wdenkc837dcb2004-01-20 23:12:12 +000072#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
73#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
stroese13fdf8a2003-09-12 08:55:18 +000074
wdenkc837dcb2004-01-20 23:12:12 +000075#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
stroese13fdf8a2003-09-12 08:55:18 +000076
stroesea20b27a2004-12-16 18:05:42 +000077#define CONFIG_PRAM 2 /* reserve 2 kB "protected RAM" */
78
stroese13fdf8a2003-09-12 08:55:18 +000079/*
80 * Miscellaneous configurable options
81 */
82#define CFG_LONGHELP /* undef to save memory */
83#define CFG_PROMPT "=> " /* Monitor Command Prompt */
84
85#undef CFG_HUSH_PARSER /* use "hush" command parser */
86#ifdef CFG_HUSH_PARSER
wdenkc837dcb2004-01-20 23:12:12 +000087#define CFG_PROMPT_HUSH_PS2 "> "
stroese13fdf8a2003-09-12 08:55:18 +000088#endif
89
90#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +000091#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +000092#else
wdenkc837dcb2004-01-20 23:12:12 +000093#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +000094#endif
95#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
96#define CFG_MAXARGS 16 /* max number of command args */
97#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
98
wdenkc837dcb2004-01-20 23:12:12 +000099#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
stroese13fdf8a2003-09-12 08:55:18 +0000100
wdenkc837dcb2004-01-20 23:12:12 +0000101#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroese13fdf8a2003-09-12 08:55:18 +0000102
103#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
104#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
105
wdenkc837dcb2004-01-20 23:12:12 +0000106#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
107#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
108#define CFG_BASE_BAUD 691200
109#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
stroese13fdf8a2003-09-12 08:55:18 +0000110
111/* The following table includes the supported baudrates */
wdenkc837dcb2004-01-20 23:12:12 +0000112#define CFG_BAUDRATE_TABLE \
stroese13fdf8a2003-09-12 08:55:18 +0000113 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
114 57600, 115200, 230400, 460800, 921600 }
115
116#define CFG_LOAD_ADDR 0x100000 /* default load address */
117#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
118
wdenkc837dcb2004-01-20 23:12:12 +0000119#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
stroese13fdf8a2003-09-12 08:55:18 +0000120
121#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
122
wdenkc837dcb2004-01-20 23:12:12 +0000123#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese13fdf8a2003-09-12 08:55:18 +0000124
wdenkc837dcb2004-01-20 23:12:12 +0000125#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese13fdf8a2003-09-12 08:55:18 +0000126
127/*-----------------------------------------------------------------------
128 * PCI stuff
129 *-----------------------------------------------------------------------
130 */
wdenkc837dcb2004-01-20 23:12:12 +0000131#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
132#define PCI_HOST_FORCE 1 /* configure as pci host */
133#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroese13fdf8a2003-09-12 08:55:18 +0000134
wdenkc837dcb2004-01-20 23:12:12 +0000135#define CONFIG_PCI /* include pci support */
136#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
137#undef CONFIG_PCI_PNP /* do pci plug-and-play */
138 /* resource configuration */
stroese13fdf8a2003-09-12 08:55:18 +0000139
wdenkc837dcb2004-01-20 23:12:12 +0000140#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroese13fdf8a2003-09-12 08:55:18 +0000141
wdenkc837dcb2004-01-20 23:12:12 +0000142#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
143#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
144#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
145#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
146#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
147#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
148#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
149#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
150#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
stroese13fdf8a2003-09-12 08:55:18 +0000151
152/*
153 * For booting Linux, the board info and command line data
154 * have to be in the first 8 MB of memory, since this is
155 * the maximum mapped by the Linux kernel during initialization.
156 */
157#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
158/*-----------------------------------------------------------------------
159 * FLASH organization
160 */
161#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
162
163#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
164#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
165
166#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
167#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
168
wdenkc837dcb2004-01-20 23:12:12 +0000169#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
170#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
171#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroese13fdf8a2003-09-12 08:55:18 +0000172/*
173 * The following defines are added for buggy IOP480 byte interface.
174 * All other boards should use the standard values (CPCI405 etc.)
175 */
wdenkc837dcb2004-01-20 23:12:12 +0000176#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
177#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
178#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
stroese13fdf8a2003-09-12 08:55:18 +0000179
wdenkc837dcb2004-01-20 23:12:12 +0000180#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroese13fdf8a2003-09-12 08:55:18 +0000181
182#if 0 /* test-only */
wdenkc837dcb2004-01-20 23:12:12 +0000183#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
184#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
stroese13fdf8a2003-09-12 08:55:18 +0000185#endif
186
187/*-----------------------------------------------------------------------
188 * Start addresses for the final memory configuration
189 * (Set up by the startup code)
190 * Please note that CFG_SDRAM_BASE _must_ start at 0
191 */
192#define CFG_SDRAM_BASE 0x00000000
193#define CFG_FLASH_BASE 0xFFFC0000
194#define CFG_MONITOR_BASE TEXT_BASE
195#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
196#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
197
198#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
199# define CFG_RAMBOOT 1
200#else
201# undef CFG_RAMBOOT
202#endif
203
204/*-----------------------------------------------------------------------
205 * Environment Variable setup
206 */
wdenkc837dcb2004-01-20 23:12:12 +0000207#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
208#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
209#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
stroese13fdf8a2003-09-12 08:55:18 +0000210 /* total size of a CAT24WC16 is 2048 bytes */
211
212#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
wdenkc837dcb2004-01-20 23:12:12 +0000213#define CFG_NVRAM_SIZE 242 /* NVRAM size */
stroese13fdf8a2003-09-12 08:55:18 +0000214
215/*-----------------------------------------------------------------------
216 * I2C EEPROM (CAT24WC16) for environment
217 */
218#define CONFIG_HARD_I2C /* I2c with hardware support */
219#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
220#define CFG_I2C_SLAVE 0x7F
221
222#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
wdenkc837dcb2004-01-20 23:12:12 +0000223#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
224/* mask of address bits that overflow into the "EEPROM chip address" */
stroese13fdf8a2003-09-12 08:55:18 +0000225#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
226#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
227 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000228 /* last 4 bits of the address */
stroese13fdf8a2003-09-12 08:55:18 +0000229#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
230#define CFG_EEPROM_PAGE_WRITE_ENABLE
231
232/*-----------------------------------------------------------------------
233 * Cache Configuration
234 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200235#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
wdenkc837dcb2004-01-20 23:12:12 +0000236 /* have only 8kB, 16kB is save here */
stroese13fdf8a2003-09-12 08:55:18 +0000237#define CFG_CACHELINE_SIZE 32 /* ... */
238#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
239#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
240#endif
241
242/*-----------------------------------------------------------------------
243 * External Bus Controller (EBC) Setup
244 */
245
wdenkc837dcb2004-01-20 23:12:12 +0000246#define CAN_BA 0xF0000000 /* CAN Base Address */
247#define RTC_BA 0xF0000500 /* RTC Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000248
wdenkc837dcb2004-01-20 23:12:12 +0000249/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
250#define CFG_EBC_PB0AP 0x92015480
251#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroese13fdf8a2003-09-12 08:55:18 +0000252
253#if 0 /* test-only */
wdenkc837dcb2004-01-20 23:12:12 +0000254/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
255#define CFG_EBC_PB1AP 0x92015480
256#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000257#endif
258
wdenkc837dcb2004-01-20 23:12:12 +0000259/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
260#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
261#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000262
263/*-----------------------------------------------------------------------
264 * FPGA stuff
265 */
wdenkc837dcb2004-01-20 23:12:12 +0000266#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
267#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
stroese13fdf8a2003-09-12 08:55:18 +0000268
269/* FPGA program pin configuration */
wdenkc837dcb2004-01-20 23:12:12 +0000270#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
271#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
272#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
273#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */
274#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
stroese13fdf8a2003-09-12 08:55:18 +0000275
276/*-----------------------------------------------------------------------
277 * Definitions for initial stack pointer and data area (in data cache)
278 */
279/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
wdenkc837dcb2004-01-20 23:12:12 +0000280#define CFG_TEMP_STACK_OCM 1
stroese13fdf8a2003-09-12 08:55:18 +0000281
282/* On Chip Memory location */
283#define CFG_OCM_DATA_ADDR 0xF8000000
284#define CFG_OCM_DATA_SIZE 0x1000
285#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
286#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
287
288#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
289#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc837dcb2004-01-20 23:12:12 +0000290#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
stroese13fdf8a2003-09-12 08:55:18 +0000291
292/*-----------------------------------------------------------------------
293 * Definitions for GPIO setup (PPC405EP specific)
294 *
wdenkc837dcb2004-01-20 23:12:12 +0000295 * GPIO0[0] - External Bus Controller BLAST output
296 * GPIO0[1-9] - Instruction trace outputs -> GPIO
stroese13fdf8a2003-09-12 08:55:18 +0000297 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
298 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
299 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
300 * GPIO0[24-27] - UART0 control signal inputs/outputs
301 * GPIO0[28-29] - UART1 data signal input/output
302 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
303 */
wdenkc837dcb2004-01-20 23:12:12 +0000304/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
305/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
306/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
stroese13fdf8a2003-09-12 08:55:18 +0000307/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
wdenkc837dcb2004-01-20 23:12:12 +0000308#define CFG_GPIO0_OSRH 0x40000540 /* 0 ... 15 */
309#define CFG_GPIO0_OSRL 0x00000110 /* 16 ... 31 */
310#define CFG_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */
311#define CFG_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */
312#define CFG_GPIO0_TSRH 0x00000000 /* 0 ... 15 */
313#define CFG_GPIO0_TSRL 0x00000000 /* 16 ... 31 */
314#define CFG_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
stroese13fdf8a2003-09-12 08:55:18 +0000315
316/*
317 * Internal Definitions
318 *
319 * Boot Flags
320 */
321#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
322#define BOOTFLAG_WARM 0x02 /* Software reboot */
323
324/*
325 * Default speed selection (cpu_plb_opb_ebc) in mhz.
326 * This value will be set if iic boot eprom is disabled.
327 */
328#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000329#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
330#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000331#endif
332#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000333#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
334#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
stroese13fdf8a2003-09-12 08:55:18 +0000335#endif
336#if 1
wdenkc837dcb2004-01-20 23:12:12 +0000337#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
338#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000339#endif
340
341#endif /* __CONFIG_H */