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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2002 ELTEC Elektronik AG
3 * Frank Gottschling <fgottschling@eltec.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
wdenke2211742002-11-02 23:30:20 +000031#undef DEBUG
32#define GTREGREAD(x) 0xffffffff /* needed for debug */
33
34/*
35 * High Level Configuration Options
36 * (easy to change)
37 */
38
39/* these hardware addresses are pretty bogus, please change them to
40 suit your needs */
41
42/* first ethernet */
43#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
44
45#define CONFIG_IPADDR 192.168.0.105
46#define CONFIG_SERVERIP 192.168.0.100
47
48#define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */
49
50#define CONFIG_BAUDRATE 9600 /* console baudrate */
51
52#undef CONFIG_WATCHDOG
53
54#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
55
56#define CONFIG_ZERO_BOOTDELAY_CHECK
57
58#undef CONFIG_BOOTARGS
59#define CONFIG_BOOTCOMMAND \
60 "bootp 1000000; " \
61 "setenv bootargs root=ramfs console=ttyS00,9600 " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
63 "${netmask}:${hostname}:eth0:none; " \
wdenke2211742002-11-02 23:30:20 +000064 "bootm"
65
66#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
67#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
68
69#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
70
71#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2)
72
73/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
74#include <cmd_confdefs.h>
75
76/*
77 * Miscellaneous configurable options
78 */
79#define CFG_LONGHELP /* undef to save memory */
80#define CFG_PROMPT "=> " /* Monitor Command Prompt */
81
82/*
83 * choose between COM1 and COM2 as serial console
84 */
85#define CONFIG_CONS_INDEX 1
86
87#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
88#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
89#else
90#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
91#endif
92#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
93#define CFG_MAXARGS 16 /* max number of command args */
94#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
95
96#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
97#define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
98
99#define CFG_LOAD_ADDR 0x1000000 /* default load address */
100
101#define CFG_HZ 1000 /* dec. freq: 1 ms ticks */
102
103#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
104
105/*
106 * Low Level Configuration Settings
107 * (address mappings, register initial values, etc.)
108 * You should know what you are doing if you make changes here.
109 */
110#define CFG_BOARD_ASM_INIT
111#define CONFIG_MISC_INIT_R
112
113/*
114 * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
115 */
116#undef CFG_ADDRESS_MAP_A
117
118#define CFG_PCI_MEMORY_BUS 0x00000000
119#define CFG_PCI_MEMORY_PHYS 0x00000000
120#define CFG_PCI_MEMORY_SIZE 0x40000000
121
122#define CFG_PCI_MEM_BUS 0x80000000
123#define CFG_PCI_MEM_PHYS 0x80000000
124#define CFG_PCI_MEM_SIZE 0x7d000000
125
126#define CFG_ISA_MEM_BUS 0x00000000
127#define CFG_ISA_MEM_PHYS 0xfd000000
128#define CFG_ISA_MEM_SIZE 0x01000000
129
130#define CFG_PCI_IO_BUS 0x00800000
131#define CFG_PCI_IO_PHYS 0xfe800000
132#define CFG_PCI_IO_SIZE 0x00400000
133
134#define CFG_ISA_IO_BUS 0x00000000
135#define CFG_ISA_IO_PHYS 0xfe000000
136#define CFG_ISA_IO_SIZE 0x00800000
137
138/* driver defines FDC,IDE,... */
139#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
140#define CFG_ISA_IO CFG_ISA_IO_PHYS
141#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
142
143/*
144 * Start addresses for the final memory configuration
145 * (Set up by the startup code)
146 * Please note that CFG_SDRAM_BASE _must_ start at 0
147 */
148#define CFG_SDRAM_BASE 0x00000000
149
150#define CFG_USR_LED_BASE 0x78000000
151#define CFG_NVRAM_BASE 0xff000000
152#define CFG_UART_BASE 0xff400000
153#define CFG_FLASH_BASE 0xfff00000
154
155#define MPC107_EUMB_ADDR 0xfce00000
156#define MPC107_EUMB_PI 0xfce41090
157#define MPC107_EUMB_GCR 0xfce41020
158#define MPC107_EUMB_IACKR 0xfce600a0
159#define MPC107_I2C_ADDR 0xfce03000
160
161/*
162 * Definitions for initial stack pointer and data area
163 */
164#define CFG_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
165#define CFG_INIT_RAM_END 0x4000
166#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */
167#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
168#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
169
170/*
171 * Flash mapping/organization on the MPC10x.
172 */
173#define FLASH_BASE0_PRELIM 0xff800000
174#define FLASH_BASE1_PRELIM 0xffc00000
175
176#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
177#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
178
179#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
180#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
181
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200182/*
183 * JFFS2 partitions
184 *
185 */
186/* No command line, one static partition, whole device */
187#undef CONFIG_JFFS2_CMDLINE
188#define CONFIG_JFFS2_DEV "nor0"
189#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
190#define CONFIG_JFFS2_PART_OFFSET 0x00000000
191
192/* mtdparts command line support */
193/* Note: fake mtd_id used, no linux mtd map file */
194/*
195#define CONFIG_JFFS2_CMDLINE
196#define MTDIDS_DEFAULT "nor0=elppc-0,nor1=elppc-1"
197#define MTDPARTS_DEFAULT "mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
198*/
wdenke2211742002-11-02 23:30:20 +0000199
200#define CFG_MONITOR_BASE CFG_FLASH_BASE
201#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
202#define CFG_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
203#undef CFG_MEMTEST
204
205/*
206 * Environment settings
207 */
208#define CONFIG_ENV_OVERWRITE
209#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
210#define CFG_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */
211#define CFG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
212#define CFG_ENV_ADDR 0x0
213#define CFG_ENV_MAP_ADRS 0xff000000
214#define CFG_NV_SROM_COPY_ADDR (CFG_ENV_ADDR + CFG_ENV_SIZE)
215#define CFG_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */
216#define CFG_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
217
218/*
219 * Serial devices
220 */
221#define CFG_NS16550
222#define CFG_NS16550_SERIAL
223#define CFG_NS16550_REG_SIZE 1
224#define CFG_NS16550_CLK 24000000
225#define CFG_NS16550_COM1 (CFG_UART_BASE + 0)
226#define CFG_NS16550_COM2 (CFG_UART_BASE + 8)
227
228/*
229 * PCI stuff
230 */
231#define CONFIG_PCI /* include pci support */
232#define CONFIG_PCI_PNP /* pci plug-and-play */
233#define CONFIG_PCI_HOST PCI_HOST_AUTO
234#undef CONFIG_PCI_SCAN_SHOW
235
236/*
237 * Optional Video console (graphic: SMI LynxEM)
238 */
239#define CONFIG_VIDEO
240#define CONFIG_CFB_CONSOLE
241#define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10))
242#define VIDEO_TSTC_FCT serial_tstc
243#define VIDEO_GETC_FCT serial_getc
244
245#define CONFIG_VIDEO_SMI_LYNXEM
246#define CONFIG_VIDEO_LOGO
247#define CONFIG_CONSOLE_EXTRA_INFO
248
249/*
250 * Initial BATs
251 */
252#if 1
253
254#define CFG_IBAT0L 0
255#define CFG_IBAT0U 0
256#define CFG_DBAT0L CFG_IBAT1L
257#define CFG_DBAT0U CFG_IBAT1U
258
259#define CFG_IBAT1L 0
260#define CFG_IBAT1U 0
261#define CFG_DBAT1L CFG_IBAT1L
262#define CFG_DBAT1U CFG_IBAT1U
263
264#define CFG_IBAT2L 0
265#define CFG_IBAT2U 0
266#define CFG_DBAT2L CFG_IBAT2L
267#define CFG_DBAT2U CFG_IBAT2U
268
269#define CFG_IBAT3L 0
270#define CFG_IBAT3U 0
271#define CFG_DBAT3L CFG_IBAT3L
272#define CFG_DBAT3U CFG_IBAT3U
273
274#else
275
276/* SDRAM */
277#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
278#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
279#define CFG_DBAT0L CFG_IBAT1L
280#define CFG_DBAT0U CFG_IBAT1U
281
282/* address range for flashes */
283#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
284#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
285#define CFG_DBAT1L CFG_IBAT1L
286#define CFG_DBAT1U CFG_IBAT1U
287
288/* ISA IO space */
289#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
290#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
291#define CFG_DBAT2L CFG_IBAT2L
292#define CFG_DBAT2U CFG_IBAT2U
293
294/* ISA memory space */
295#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
296#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
297#define CFG_DBAT3L CFG_IBAT3L
298#define CFG_DBAT3U CFG_IBAT3U
299
300#endif
301
302/*
303 * Speed settings are board specific
304 */
305#define CFG_BUS_HZ 100000000
306#define CFG_CPU_CLK 400000000
307#define CFG_BUS_CLK CFG_BUS_HZ
308
309/*
310 * For booting Linux, the board info and command line data
311 * have to be in the first 8 MB of memory, since this is
312 * the maximum mapped by the Linux kernel during initialization.
313 */
314#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
315
316/*
317 * Cache Configuration
318 */
319#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
320#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
321#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
322#endif
323
324/*
325 * L2CR setup -- make sure this is right for your board!
wdenk1d0350e2002-11-11 21:14:20 +0000326 * look in include/74xx_7xx.h for the defines used here
wdenke2211742002-11-02 23:30:20 +0000327 */
328
329#define CFG_L2
330
331#if 1
332#define L2_INIT 0 /* cpu 750 CXe*/
333#else
334#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
wdenk8bde7f72003-06-27 21:31:46 +0000335 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
wdenke2211742002-11-02 23:30:20 +0000336#endif
337#define L2_ENABLE (L2_INIT | L2CR_L2E)
338
339/*
340 * Internal Definitions
341 *
342 * Boot Flags
343 */
344#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
345#define BOOTFLAG_WARM 0x02 /* Software reboot */
346
347#define CONFIG_NET_MULTI /* Multi ethernet cards support */
348#define CONFIG_EEPRO100
stroese53cf9432003-06-05 15:39:44 +0000349#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenke2211742002-11-02 23:30:20 +0000350#define CONFIG_EEPRO100_SROM_WRITE
351
352#endif /* __CONFIG_H */