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Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +01001/*
2 * Configuation settings for the Delta board.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26/*
27 * High Level Configuration Options
28 * (easy to change)
29 */
30#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
31#define CONFIG_DELTA 1 /* Delta board */
32
33/* #define CONFIG_LCD 1 */
34#ifdef CONFIG_LCD
35#define CONFIG_SHARP_LM8V31
36#endif
37/* #define CONFIG_MMC 1 */
38#define BOARD_LATE_INIT 1
39
40#undef CONFIG_SKIP_RELOCATE_UBOOT
41#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
42
43/*
44 * Size of malloc() pool
45 */
Markus Klotzbücherf9e02912006-03-06 13:45:42 +010046#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +010047#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
48
49/*
50 * Hardware drivers
51 */
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +010052#undef TURN_ON_ETHERNET
53#ifdef TURN_ON_ETHERNET
54# define CONFIG_DRIVER_SMC91111 1
55# define CONFIG_SMC91111_BASE 0x14000300
56# define CONFIG_SMC91111_EXT_PHY
57# define CONFIG_SMC_USE_32_BIT
58# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
59#endif
60
Markus Klotzbuecherba70d6a2006-03-24 12:23:27 +010061#define CONFIG_HARD_I2C 1 /* required for DA9030 access */
62#define CFG_I2C_SPEED 400000 /* I2C speed */
63#define CFG_I2C_SLAVE 1 /* I2C controllers address */
64#define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */
Markus Klotzbuecher89f2dfa2006-03-29 17:49:27 +020065#define CFG_DA9030_EXTON_DELAY 100000 /* wait x us after DA9030 reset via EXTON */
Markus Klotzbuecher9e7b5ce2006-03-30 17:00:39 +020066#define CFG_I2C_INIT_BOARD 1
Markus Klotzbuecherba70d6a2006-03-24 12:23:27 +010067/* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */
68
Markus Klotzbuecher71ae4112006-04-25 10:03:01 +020069#define DELTA_CHECK_KEYBD 1 /* check for keys pressed during boot */
70#define CONFIG_PREBOOT "\0"
71
72#ifdef DELTA_CHECK_KEYBD
73# define KEYBD_DATALEN 4 /* we have four keys */
74# define KEYBD_KP_DKIN0 0x1 /* vol+ */
75# define KEYBD_KP_DKIN1 0x2 /* vol- */
76# define KEYBD_KP_DKIN2 0x3 /* multi */
77# define KEYBD_KP_DKIN5 0x4 /* SWKEY_GN */
78#endif /* DELTA_CHECK_KEYBD */
79
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +010080/*
81 * select serial console configuration
82 */
Markus Klotzbuecher552fc622006-03-20 20:19:37 +010083#define CONFIG_FFUART 1
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +010084
85/* allow to overwrite serial and ethaddr */
86#define CONFIG_ENV_OVERWRITE
87
88#define CONFIG_BAUDRATE 115200
89
90/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */
91#ifdef TURN_ON_ETHERNET
92# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
93#else
Markus Klotzbuecherba70d6a2006-03-24 12:23:27 +010094# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
95 | CFG_CMD_ENV \
96 | CFG_CMD_NAND \
97 | CFG_CMD_I2C) \
98 & ~(CFG_CMD_NET \
99 | CFG_CMD_FLASH \
100 | CFG_CMD_IMLS))
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100101#endif
102
103
104/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
105#include <cmd_confdefs.h>
106
107#define CONFIG_BOOTDELAY -1
108#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
109#define CONFIG_NETMASK 255.255.0.0
110#define CONFIG_IPADDR 192.168.0.21
111#define CONFIG_SERVERIP 192.168.0.250
112#define CONFIG_BOOTCOMMAND "bootm 80000"
113#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
114#define CONFIG_CMDLINE_TAG
115#define CONFIG_TIMESTAMP
116
117#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
118#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
119#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
120#endif
121
122/*
123 * Miscellaneous configurable options
124 */
125#define CFG_HUSH_PARSER 1
126#define CFG_PROMPT_HUSH_PS2 "> "
127
128#define CFG_LONGHELP /* undef to save memory */
129#ifdef CFG_HUSH_PARSER
130#define CFG_PROMPT "$ " /* Monitor Command Prompt */
131#else
132#define CFG_PROMPT "=> " /* Monitor Command Prompt */
133#endif
134#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
135#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
136#define CFG_MAXARGS 16 /* max number of command args */
137#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
138#define CFG_DEVICE_NULLDEV 1
139
Markus Klotzbuechereeaab722006-03-29 17:59:20 +0200140#define CFG_MEMTEST_START 0x80400000 /* memtest works on */
141#define CFG_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100142
143#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
144
145#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */
146
Markus Klotzbuecherba70d6a2006-03-24 12:23:27 +0100147#define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */
Markus Klotzbuecher40b0baf2006-03-24 14:35:25 +0100148
Markus Klotzbuecherc855ef62006-03-27 16:01:03 +0200149/* Monahans Core Frequency */
Markus Klotzbuecher40b0baf2006-03-24 14:35:25 +0100150#define CFG_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
151#define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */
152
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100153
154 /* valid baudrates */
155#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
156
157/* #define CFG_MMC_BASE 0xF0000000 */
158
159/*
160 * Stack sizes
161 *
162 * The stack sizes are set up in start.S using the settings below
163 */
164#define CONFIG_STACKSIZE (128*1024) /* regular stack */
165#ifdef CONFIG_USE_IRQ
166#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
167#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
168#endif
169
170/*
171 * Physical Memory Map
172 */
173#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
Markus Klotzbuechereeaab722006-03-29 17:59:20 +0200174#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
Markus Klotzbücher599f5222006-02-22 17:48:43 +0100175#define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */
Markus Klotzbuechereeaab722006-03-29 17:59:20 +0200176#define PHYS_SDRAM_2 0x81000000 /* SDRAM Bank #2 */
Markus Klotzbücher599f5222006-02-22 17:48:43 +0100177#define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */
Markus Klotzbuechereeaab722006-03-29 17:59:20 +0200178#define PHYS_SDRAM_3 0x82000000 /* SDRAM Bank #3 */
Markus Klotzbücher599f5222006-02-22 17:48:43 +0100179#define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */
Markus Klotzbuechereeaab722006-03-29 17:59:20 +0200180#define PHYS_SDRAM_4 0x83000000 /* SDRAM Bank #4 */
Markus Klotzbücher599f5222006-02-22 17:48:43 +0100181#define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100182
Markus Klotzbuechereeaab722006-03-29 17:59:20 +0200183#define CFG_DRAM_BASE 0x80000000 /* at CS0 */
Markus Klotzbücher599f5222006-02-22 17:48:43 +0100184#define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */
Markus Klotzbücherff3c2a92006-02-22 14:05:44 +0100185
Markus Klotzbücherac7d97d2006-03-06 18:47:44 +0100186#undef CFG_SKIP_DRAM_SCRUB
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100187
Markus Klotzbücher69493282006-02-28 18:05:25 +0100188/*
189 * NAND Flash
190 */
191/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
Marian Balakowicz6db39702006-04-08 19:08:06 +0200192#undef CFG_NAND_LEGACY
193
Markus Klotzbücherf9e02912006-03-06 13:45:42 +0100194#define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
Markus Klotzbücher69493282006-02-28 18:05:25 +0100195#undef CFG_NAND1_BASE
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100196
Markus Klotzbücher69493282006-02-28 18:05:25 +0100197#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
198#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Markus Klotzbücher69493282006-02-28 18:05:25 +0100199
Wolfgang Denk951a9542006-03-06 23:18:48 +0100200/* nand timeout values */
Markus Klotzbücherf9e02912006-03-06 13:45:42 +0100201#define CFG_NAND_PROG_ERASE_TO 3000
Markus Klotzbücherbf7cac02006-03-04 18:35:51 +0100202#define CFG_NAND_OTHER_TO 100
203#define CFG_NAND_SENDCMD_RETRY 3
Markus Klotzbücher43638c62006-03-06 15:04:25 +0100204#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
205
206/* NAND Timing Parameters (in ns) */
Markus Klotzbuecher552fc622006-03-20 20:19:37 +0100207#define NAND_TIMING_tCH 10
208#define NAND_TIMING_tCS 0
Markus Klotzbücher43638c62006-03-06 15:04:25 +0100209#define NAND_TIMING_tWH 20
Markus Klotzbuecher552fc622006-03-20 20:19:37 +0100210#define NAND_TIMING_tWP 40
Markus Klotzbücher43638c62006-03-06 15:04:25 +0100211
Markus Klotzbuecher552fc622006-03-20 20:19:37 +0100212#define NAND_TIMING_tRH 20
213#define NAND_TIMING_tRP 40
Markus Klotzbücher43638c62006-03-06 15:04:25 +0100214
Markus Klotzbuecher552fc622006-03-20 20:19:37 +0100215#define NAND_TIMING_tR 11123
Markus Klotzbücher43638c62006-03-06 15:04:25 +0100216#define NAND_TIMING_tWHR 100
217#define NAND_TIMING_tAR 10
218
219/* NAND debugging */
220#define CFG_DFC_DEBUG1 /* usefull */
221#undef CFG_DFC_DEBUG2 /* noisy */
222#undef CFG_DFC_DEBUG3 /* extremly noisy */
Markus Klotzbücherf9e02912006-03-06 13:45:42 +0100223
224#define CONFIG_MTD_DEBUG
225#define CONFIG_MTD_DEBUG_VERBOSE 1
Markus Klotzbücherbf7cac02006-03-04 18:35:51 +0100226
Markus Klotzbuecher552fc622006-03-20 20:19:37 +0100227#define ADDR_COLUMN 1
228#define ADDR_PAGE 2
229#define ADDR_COLUMN_PAGE 3
Markus Klotzbücher69493282006-02-28 18:05:25 +0100230
231#define NAND_ChipID_UNKNOWN 0x00
Markus Klotzbuecher552fc622006-03-20 20:19:37 +0100232#define NAND_MAX_FLOORS 1
233#define NAND_MAX_CHIPS 1
Markus Klotzbücher69493282006-02-28 18:05:25 +0100234
Markus Klotzbuecher552fc622006-03-20 20:19:37 +0100235#define CFG_NO_FLASH 1
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100236
Markus Klotzbücher8371a2c2006-03-08 00:13:40 +0100237#define CFG_ENV_IS_IN_NAND 1
Markus Klotzbücher69493282006-02-28 18:05:25 +0100238#define CFG_ENV_OFFSET 0x40000
Markus Klotzbuechere443c942006-03-20 18:02:44 +0100239#define CFG_ENV_OFFSET_REDUND 0x44000
Markus Klotzbücher69493282006-02-28 18:05:25 +0100240#define CFG_ENV_SIZE 0x4000
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100241
242#endif /* __CONFIG_H */