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wdenk71f95112003-06-15 22:40:42 +00001/*
Wolfgang Denk23c5d252014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenk71f95112003-06-15 22:40:42 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk71f95112003-06-15 22:40:42 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC860 1
21#define CONFIG_MPC860T 1
22#define CONFIG_MPC862 1
Wolfgang Denk23c5d252014-10-24 15:31:26 +020023#define CONFIG_SYS_GENERIC_BOARD
24#define CONFIG_DISPLAY_BOARDINFO
wdenk71f95112003-06-15 22:40:42 +000025
26#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */
27
Wolfgang Denk2ae18242010-10-06 09:05:45 +020028#define CONFIG_SYS_TEXT_BASE 0x40000000
29
wdenk71f95112003-06-15 22:40:42 +000030#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020031#define CONFIG_SYS_SMC_RXBUFLEN 128
32#define CONFIG_SYS_MAXIDLE 10
wdenk71f95112003-06-15 22:40:42 +000033#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
34
wdenkae3af052003-08-07 22:18:11 +000035#define CONFIG_BOOTCOUNT_LIMIT
wdenk71f95112003-06-15 22:40:42 +000036
wdenkae3af052003-08-07 22:18:11 +000037#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk71f95112003-06-15 22:40:42 +000038
39#define CONFIG_BOARD_TYPES 1 /* support board types */
40
41#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010042 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk71f95112003-06-15 22:40:42 +000043 "echo"
44
45#undef CONFIG_BOOTARGS
46
47#define CONFIG_EXTRA_ENV_SETTINGS \
48 "netdev=eth0\0" \
49 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010050 "nfsroot=${serverip}:${rootpath}\0" \
wdenk71f95112003-06-15 22:40:42 +000051 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010052 "addip=setenv bootargs ${bootargs} " \
53 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
54 ":${hostname}:${netdev}:off panic=1\0" \
wdenk71f95112003-06-15 22:40:42 +000055 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010056 "bootm ${kernel_addr}\0" \
wdenk71f95112003-06-15 22:40:42 +000057 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010058 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
59 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk71f95112003-06-15 22:40:42 +000060 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020061 "hostname=TQM862M\0" \
62 "bootfile=TQM862M/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020063 "fdt_addr=40080000\0" \
64 "kernel_addr=400A0000\0" \
65 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020066 "u-boot=TQM862M/u-image.bin\0" \
67 "load=tftp 200000 ${u-boot}\0" \
68 "update=prot off 40000000 +${filesize};" \
69 "era 40000000 +${filesize};" \
70 "cp.b 200000 40000000 ${filesize};" \
71 "sete filesize;save\0" \
wdenk71f95112003-06-15 22:40:42 +000072 ""
73#define CONFIG_BOOTCOMMAND "run flash_self"
74
75#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk71f95112003-06-15 22:40:42 +000077
78#undef CONFIG_WATCHDOG /* watchdog disabled */
79
80#define CONFIG_STATUS_LED 1 /* Status LED enabled */
81
82#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
83
Jon Loeliger37d4bb72007-07-09 21:38:02 -050084/*
85 * BOOTP options
86 */
87#define CONFIG_BOOTP_SUBNETMASK
88#define CONFIG_BOOTP_GATEWAY
89#define CONFIG_BOOTP_HOSTNAME
90#define CONFIG_BOOTP_BOOTPATH
91#define CONFIG_BOOTP_BOOTFILESIZE
92
wdenk71f95112003-06-15 22:40:42 +000093
94#define CONFIG_MAC_PARTITION
95#define CONFIG_DOS_PARTITION
96
97#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
98
wdenk71f95112003-06-15 22:40:42 +000099
Jon Loeliger26946902007-07-04 22:30:50 -0500100/*
101 * Command line configuration.
102 */
Jon Loeliger26946902007-07-04 22:30:50 -0500103#define CONFIG_CMD_ASKENV
104#define CONFIG_CMD_DATE
105#define CONFIG_CMD_DHCP
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200106#define CONFIG_CMD_ELF
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100107#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500108#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200109#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500110#define CONFIG_CMD_SNTP
111
wdenk71f95112003-06-15 22:40:42 +0000112
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200113#define CONFIG_NETCONSOLE
114
115
wdenk71f95112003-06-15 22:40:42 +0000116/*
117 * Miscellaneous configurable options
118 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk71f95112003-06-15 22:40:42 +0000120
Wolfgang Denk2751a952006-10-28 02:29:14 +0200121#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
wdenk71f95112003-06-15 22:40:42 +0000123
Jon Loeliger26946902007-07-04 22:30:50 -0500124#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk71f95112003-06-15 22:40:42 +0000126#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk71f95112003-06-15 22:40:42 +0000128#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
130#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
131#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk71f95112003-06-15 22:40:42 +0000132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
134#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk71f95112003-06-15 22:40:42 +0000135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk71f95112003-06-15 22:40:42 +0000137
wdenk71f95112003-06-15 22:40:42 +0000138/*
139 * Low Level Configuration Settings
140 * (address mappings, register initial values, etc.)
141 * You should know what you are doing if you make changes here.
142 */
143/*-----------------------------------------------------------------------
144 * Internal Memory Mapped Register
145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_IMMR 0xFFF00000
wdenk71f95112003-06-15 22:40:42 +0000147
148/*-----------------------------------------------------------------------
149 * Definitions for initial stack pointer and data area (in DPRAM)
150 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200152#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200153#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk71f95112003-06-15 22:40:42 +0000155
156/*-----------------------------------------------------------------------
157 * Start addresses for the final memory configuration
158 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk71f95112003-06-15 22:40:42 +0000160 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_SDRAM_BASE 0x00000000
162#define CONFIG_SYS_FLASH_BASE 0x40000000
163#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
164#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
165#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk71f95112003-06-15 22:40:42 +0000166
167/*
168 * For booting Linux, the board info and command line data
169 * have to be in the first 8 MB of memory, since this is
170 * the maximum mapped by the Linux kernel during initialization.
171 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk71f95112003-06-15 22:40:42 +0000173
174/*-----------------------------------------------------------------------
175 * FLASH organization
176 */
wdenk71f95112003-06-15 22:40:42 +0000177
Martin Krausee318d9e2007-09-27 11:10:08 +0200178/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200180#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
182#define CONFIG_SYS_FLASH_EMPTY_INFO
183#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
184#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
185#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk71f95112003-06-15 22:40:42 +0000186
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200187#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200188#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
189#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
190#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
wdenk71f95112003-06-15 22:40:42 +0000191
192/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200193#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
194#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenk71f95112003-06-15 22:40:42 +0000195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200197
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200198#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
199
wdenk71f95112003-06-15 22:40:42 +0000200/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200201 * Dynamic MTD partition support
202 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100203#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200204#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
205#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200206#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
207
208#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
209 "128k(dtb)," \
210 "1920k(kernel)," \
211 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200212 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200213
214/*-----------------------------------------------------------------------
wdenk71f95112003-06-15 22:40:42 +0000215 * Hardware Information Block
216 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
218#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
219#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenk71f95112003-06-15 22:40:42 +0000220
221/*-----------------------------------------------------------------------
222 * Cache Configuration
223 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500225#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk71f95112003-06-15 22:40:42 +0000227#endif
228
229/*-----------------------------------------------------------------------
230 * SYPCR - System Protection Control 11-9
231 * SYPCR can only be written once after reset!
232 *-----------------------------------------------------------------------
233 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
234 */
235#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk71f95112003-06-15 22:40:42 +0000237 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
238#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk71f95112003-06-15 22:40:42 +0000240#endif
241
242/*-----------------------------------------------------------------------
243 * SIUMCR - SIU Module Configuration 11-6
244 *-----------------------------------------------------------------------
245 * PCMCIA config., multi-function pin tri-state
246 */
247#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk71f95112003-06-15 22:40:42 +0000249#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk71f95112003-06-15 22:40:42 +0000251#endif /* CONFIG_CAN_DRIVER */
252
253/*-----------------------------------------------------------------------
254 * TBSCR - Time Base Status and Control 11-26
255 *-----------------------------------------------------------------------
256 * Clear Reference Interrupt Status, Timebase freezing enabled
257 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk71f95112003-06-15 22:40:42 +0000259
260/*-----------------------------------------------------------------------
261 * RTCSC - Real-Time Clock Status and Control Register 11-27
262 *-----------------------------------------------------------------------
263 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk71f95112003-06-15 22:40:42 +0000265
266/*-----------------------------------------------------------------------
267 * PISCR - Periodic Interrupt Status and Control 11-31
268 *-----------------------------------------------------------------------
269 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
270 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk71f95112003-06-15 22:40:42 +0000272
273/*-----------------------------------------------------------------------
274 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
275 *-----------------------------------------------------------------------
276 * Reset PLL lock status sticky bit, timer expired status bit and timer
277 * interrupt status bit
wdenk71f95112003-06-15 22:40:42 +0000278 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenk71f95112003-06-15 22:40:42 +0000280
281/*-----------------------------------------------------------------------
282 * SCCR - System Clock and reset Control Register 15-27
283 *-----------------------------------------------------------------------
284 * Set clock output, timebase and RTC source and divider,
285 * power management and some other internal clocks
286 */
287#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenk71f95112003-06-15 22:40:42 +0000289 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
290 SCCR_DFALCD00)
wdenk71f95112003-06-15 22:40:42 +0000291
292/*-----------------------------------------------------------------------
293 * PCMCIA stuff
294 *-----------------------------------------------------------------------
295 *
296 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
298#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
299#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
300#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
301#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
302#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
303#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
304#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk71f95112003-06-15 22:40:42 +0000305
306/*-----------------------------------------------------------------------
307 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
308 *-----------------------------------------------------------------------
309 */
310
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000311#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenk71f95112003-06-15 22:40:42 +0000312#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
313
314#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
315#undef CONFIG_IDE_LED /* LED for ide not supported */
316#undef CONFIG_IDE_RESET /* reset for ide not supported */
317
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
319#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk71f95112003-06-15 22:40:42 +0000320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk71f95112003-06-15 22:40:42 +0000322
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk71f95112003-06-15 22:40:42 +0000324
325/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk71f95112003-06-15 22:40:42 +0000327
328/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk71f95112003-06-15 22:40:42 +0000330
331/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk71f95112003-06-15 22:40:42 +0000333
334/*-----------------------------------------------------------------------
335 *
336 *-----------------------------------------------------------------------
337 *
338 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_DER 0
wdenk71f95112003-06-15 22:40:42 +0000340
341/*
342 * Init Memory Controller:
343 *
344 * BR0/1 and OR0/1 (FLASH)
345 */
346
347#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
348#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
349
350/* used to re-map FLASH both when starting from SRAM or FLASH:
351 * restrict access enough to keep SRAM working (if any)
352 * but not too much to meddle with FLASH accesses
353 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
355#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenk71f95112003-06-15 22:40:42 +0000356
357/*
358 * FLASH timing:
359 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenk71f95112003-06-15 22:40:42 +0000361 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenk71f95112003-06-15 22:40:42 +0000362
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
364#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
365#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenk71f95112003-06-15 22:40:42 +0000366
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
368#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
369#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenk71f95112003-06-15 22:40:42 +0000370
371/*
372 * BR2/3 and OR2/3 (SDRAM)
373 *
374 */
375#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
376#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
377#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
378
379/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenk71f95112003-06-15 22:40:42 +0000381
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
383#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk71f95112003-06-15 22:40:42 +0000384
385#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
387#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk71f95112003-06-15 22:40:42 +0000388#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
390#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
391#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
392#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenk71f95112003-06-15 22:40:42 +0000393 BR_PS_8 | BR_MS_UPMB | BR_V )
394#endif /* CONFIG_CAN_DRIVER */
395
396/*
397 * Memory Periodic Timer Prescaler
398 *
399 * The Divider for PTA (refresh timer) configuration is based on an
400 * example SDRAM configuration (64 MBit, one bank). The adjustment to
401 * the number of chip selects (NCS) and the actually needed refresh
402 * rate is done by setting MPTPR.
403 *
404 * PTA is calculated from
405 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
406 *
407 * gclk CPU clock (not bus clock!)
408 * Trefresh Refresh cycle * 4 (four word bursts used)
409 *
410 * 4096 Rows from SDRAM example configuration
411 * 1000 factor s -> ms
412 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
413 * 4 Number of refresh cycles per period
414 * 64 Refresh cycle in ms per number of rows
415 * --------------------------------------------
416 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
417 *
418 * 50 MHz => 50.000.000 / Divider = 98
419 * 66 Mhz => 66.000.000 / Divider = 129
420 * 80 Mhz => 80.000.000 / Divider = 156
421 * 100 Mhz => 100.000.000 / Divider = 195
422 */
wdenke9132ea2004-04-24 23:23:30 +0000423
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
425#define CONFIG_SYS_MAMR_PTA 98
wdenk71f95112003-06-15 22:40:42 +0000426
427/*
428 * For 16 MBit, refresh rates could be 31.3 us
429 * (= 64 ms / 2K = 125 / quad bursts).
430 * For a simpler initialization, 15.6 us is used instead.
431 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
433 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenk71f95112003-06-15 22:40:42 +0000434 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
436#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk71f95112003-06-15 22:40:42 +0000437
438/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
440#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk71f95112003-06-15 22:40:42 +0000441
442/*
443 * MAMR settings for SDRAM
444 */
445
446/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk71f95112003-06-15 22:40:42 +0000448 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
449 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
450/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk71f95112003-06-15 22:40:42 +0000452 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
453 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
454
wdenk71f95112003-06-15 22:40:42 +0000455#define CONFIG_SCC1_ENET
456#define CONFIG_FEC_ENET
Heiko Schocher48690d82010-07-20 17:45:02 +0200457#define CONFIG_ETHPRIME "SCC"
wdenk71f95112003-06-15 22:40:42 +0000458
Heiko Schocher7026ead2010-02-09 15:50:27 +0100459/* pass open firmware flat tree */
460#define CONFIG_OF_LIBFDT 1
461#define CONFIG_OF_BOARD_SETUP 1
462#define CONFIG_HWCONFIG 1
463
wdenk71f95112003-06-15 22:40:42 +0000464#endif /* __CONFIG_H */