blob: a6ef356ad888a9c07c6ba3291738e4775736528f [file] [log] [blame]
York Sun7288c2c2015-03-20 19:28:23 -07001/*
2 * Copyright 2015 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS2_QDS_H
8#define __LS2_QDS_H
9
10#include "ls2085a_common.h"
York Sun7288c2c2015-03-20 19:28:23 -070011
York Sun7288c2c2015-03-20 19:28:23 -070012#define CONFIG_DISPLAY_BOARDINFO
13
14#ifndef __ASSEMBLY__
15unsigned long get_board_sys_clk(void);
16unsigned long get_board_ddr_clk(void);
17#endif
18
19#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
20#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
21#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
22
23#define CONFIG_DDR_SPD
24#define CONFIG_DDR_ECC
25#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
26#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
27#define SPD_EEPROM_ADDRESS1 0x51
28#define SPD_EEPROM_ADDRESS2 0x52
29#define SPD_EEPROM_ADDRESS3 0x53
30#define SPD_EEPROM_ADDRESS4 0x54
31#define SPD_EEPROM_ADDRESS5 0x55
32#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
33#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
34#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
35#define CONFIG_DIMM_SLOTS_PER_CTLR 2
36#define CONFIG_CHIP_SELECTS_PER_CTRL 4
37#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
38#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
39
40/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
41
42#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
43#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
44#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
45
46#define CONFIG_SYS_NOR0_CSPR \
47 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
48 CSPR_PORT_SIZE_16 | \
49 CSPR_MSEL_NOR | \
50 CSPR_V)
51#define CONFIG_SYS_NOR0_CSPR_EARLY \
52 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
53 CSPR_PORT_SIZE_16 | \
54 CSPR_MSEL_NOR | \
55 CSPR_V)
56#define CONFIG_SYS_NOR1_CSPR \
57 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
58 CSPR_PORT_SIZE_16 | \
59 CSPR_MSEL_NOR | \
60 CSPR_V)
61#define CONFIG_SYS_NOR1_CSPR_EARLY \
62 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
63 CSPR_PORT_SIZE_16 | \
64 CSPR_MSEL_NOR | \
65 CSPR_V)
66#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
67#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
68 FTIM0_NOR_TEADC(0x5) | \
69 FTIM0_NOR_TEAHC(0x5))
70#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
71 FTIM1_NOR_TRAD_NOR(0x1a) |\
72 FTIM1_NOR_TSEQRAD_NOR(0x13))
73#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
74 FTIM2_NOR_TCH(0x4) | \
75 FTIM2_NOR_TWPH(0x0E) | \
76 FTIM2_NOR_TWP(0x1c))
77#define CONFIG_SYS_NOR_FTIM3 0x04000000
78#define CONFIG_SYS_IFC_CCR 0x01000000
79
80#ifndef CONFIG_SYS_NO_FLASH
81#define CONFIG_FLASH_CFI_DRIVER
82#define CONFIG_SYS_FLASH_CFI
83#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
84#define CONFIG_SYS_FLASH_QUIET_TEST
85#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
86
87#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
88#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
89#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
90#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
91
92#define CONFIG_SYS_FLASH_EMPTY_INFO
93#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
94 CONFIG_SYS_FLASH_BASE + 0x40000000}
95#endif
96
97#define CONFIG_NAND_FSL_IFC
98#define CONFIG_SYS_NAND_MAX_ECCPOS 256
99#define CONFIG_SYS_NAND_MAX_OOBFREE 2
100
101
102#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
103#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
104 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
105 | CSPR_MSEL_NAND /* MSEL = NAND */ \
106 | CSPR_V)
107#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
108
109#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
110 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
111 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
112 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
113 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
114 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
115 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
116
117#define CONFIG_SYS_NAND_ONFI_DETECTION
118
119/* ONFI NAND Flash mode0 Timing Params */
120#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
121 FTIM0_NAND_TWP(0x18) | \
122 FTIM0_NAND_TWCHT(0x07) | \
123 FTIM0_NAND_TWH(0x0a))
124#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
125 FTIM1_NAND_TWBE(0x39) | \
126 FTIM1_NAND_TRR(0x0e) | \
127 FTIM1_NAND_TRP(0x18))
128#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
129 FTIM2_NAND_TREH(0x0a) | \
130 FTIM2_NAND_TWHRE(0x1e))
131#define CONFIG_SYS_NAND_FTIM3 0x0
132
133#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
134#define CONFIG_SYS_MAX_NAND_DEVICE 1
135#define CONFIG_MTD_NAND_VERIFY_WRITE
136#define CONFIG_CMD_NAND
137
138#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
139
140#define CONFIG_FSL_QIXIS /* use common QIXIS code */
141#define QIXIS_LBMAP_SWITCH 0x06
142#define QIXIS_LBMAP_MASK 0x0f
143#define QIXIS_LBMAP_SHIFT 0
144#define QIXIS_LBMAP_DFLTBANK 0x00
145#define QIXIS_LBMAP_ALTBANK 0x04
Scott Woodb2d5ac52015-03-24 13:25:02 -0700146#define QIXIS_LBMAP_NAND 0x09
York Sun7288c2c2015-03-20 19:28:23 -0700147#define QIXIS_RST_CTL_RESET 0x31
148#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
149#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
150#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Scott Woodb2d5ac52015-03-24 13:25:02 -0700151#define QIXIS_RCW_SRC_NAND 0x107
York Sun7288c2c2015-03-20 19:28:23 -0700152#define QIXIS_RST_FORCE_MEM 0x01
153
154#define CONFIG_SYS_CSPR3_EXT (0x0)
155#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
156 | CSPR_PORT_SIZE_8 \
157 | CSPR_MSEL_GPCM \
158 | CSPR_V)
159#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
160 | CSPR_PORT_SIZE_8 \
161 | CSPR_MSEL_GPCM \
162 | CSPR_V)
163
164#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
165#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
166/* QIXIS Timing parameters for IFC CS3 */
167#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
168 FTIM0_GPCM_TEADC(0x0e) | \
169 FTIM0_GPCM_TEAHC(0x0e))
170#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
171 FTIM1_GPCM_TRAD(0x3f))
172#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
173 FTIM2_GPCM_TCH(0xf) | \
174 FTIM2_GPCM_TWP(0x3E))
175#define CONFIG_SYS_CS3_FTIM3 0x0
176
Scott Woodb2d5ac52015-03-24 13:25:02 -0700177#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
178#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
179#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
180#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
181#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
182#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
183#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
184#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
185#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
186#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
187#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
188#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
189#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
190#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
191#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
192#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
193#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
194#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
195#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
196#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
197#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
198#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
199#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
200#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
201#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
202#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
203#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
204#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
205
206#define CONFIG_ENV_IS_IN_NAND
207#define CONFIG_ENV_OFFSET (896 * 1024)
208#define CONFIG_ENV_SECT_SIZE 0x20000
209#define CONFIG_ENV_SIZE 0x2000
210#define CONFIG_SPL_PAD_TO 0x20000
211#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
212#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
213#else
York Sun7288c2c2015-03-20 19:28:23 -0700214#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
215#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
216#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
217#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
218#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
219#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
220#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
221#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
222#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
223#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
224#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
225#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
226#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
227#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
228#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
229#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
230#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
231#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
232#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
233#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
234#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
235#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
236#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
237#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
238#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
239#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
240#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
241
Scott Woodb2d5ac52015-03-24 13:25:02 -0700242#define CONFIG_ENV_IS_IN_FLASH
243#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
244#define CONFIG_ENV_SECT_SIZE 0x20000
245#define CONFIG_ENV_SIZE 0x2000
246#endif
247
York Sun7288c2c2015-03-20 19:28:23 -0700248/* Debug Server firmware */
249#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
250#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
251
252/* MC firmware */
253#define CONFIG_SYS_LS_MC_FW_IN_NOR
254#define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL
255
256#define CONFIG_SYS_LS_MC_DPL_IN_NOR
257#define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL
258
259#define CONFIG_SYS_LS_MC_DPC_IN_NOR
260#define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL
261
262#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
J. German Riverac1000c12015-07-02 11:28:58 +0530263#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
264#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x580900000ULL
York Sun7288c2c2015-03-20 19:28:23 -0700265
266/*
267 * I2C
268 */
269#define I2C_MUX_PCA_ADDR 0x77
270#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
271
272/* I2C bus multiplexer */
273#define I2C_MUX_CH_DEFAULT 0x8
274
Haikun Wangb7774b02015-07-03 16:51:34 +0800275/* SPI */
276#ifdef CONFIG_FSL_DSPI
277#define CONFIG_CMD_SF
278#define CONFIG_SPI_FLASH
279#define CONFIG_SPI_FLASH_STMICRO
280#define CONFIG_SPI_FLASH_SST
281#define CONFIG_SPI_FLASH_EON
282#endif
283
York Sun7288c2c2015-03-20 19:28:23 -0700284/*
Yangbo Lu8b064602015-03-20 19:28:31 -0700285 * MMC
286 */
287#ifdef CONFIG_MMC
288#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
289 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
290#endif
291
292/*
York Sun7288c2c2015-03-20 19:28:23 -0700293 * RTC configuration
294 */
295#define RTC
296#define CONFIG_RTC_DS3231 1
297#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Priyanka Jain65814402015-05-28 14:53:56 +0530298#define CONFIG_CMD_DATE
York Sun7288c2c2015-03-20 19:28:23 -0700299
300/* EEPROM */
301#define CONFIG_ID_EEPROM
302#define CONFIG_CMD_EEPROM
303#define CONFIG_SYS_I2C_EEPROM_NXID
304#define CONFIG_SYS_EEPROM_BUS_NUM 0
305#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
306#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
307#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
308#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
309
York Sun7288c2c2015-03-20 19:28:23 -0700310#define CONFIG_FSL_MEMAC
311#define CONFIG_PCI /* Enable PCIE */
312#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
313
314#ifdef CONFIG_PCI
York Sun7288c2c2015-03-20 19:28:23 -0700315#define CONFIG_PCI_PNP
316#define CONFIG_E1000
317#define CONFIG_PCI_SCAN_SHOW
318#define CONFIG_CMD_PCI
York Sun7288c2c2015-03-20 19:28:23 -0700319#endif
320
Yangbo Lu8b064602015-03-20 19:28:31 -0700321/* MMC */
322#define CONFIG_MMC
323#ifdef CONFIG_MMC
324#define CONFIG_CMD_MMC
325#define CONFIG_FSL_ESDHC
326#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
327#define CONFIG_GENERIC_MMC
328#define CONFIG_CMD_FAT
329#define CONFIG_DOS_PARTITION
330#endif
York Sun7288c2c2015-03-20 19:28:23 -0700331
332/* Initial environment variables */
333#undef CONFIG_EXTRA_ENV_SETTINGS
334#define CONFIG_EXTRA_ENV_SETTINGS \
335 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
336 "loadaddr=0x80100000\0" \
337 "kernel_addr=0x100000\0" \
338 "ramdisk_addr=0x800000\0" \
339 "ramdisk_size=0x2000000\0" \
340 "fdt_high=0xa0000000\0" \
341 "initrd_high=0xffffffffffffffff\0" \
342 "kernel_start=0x581100000\0" \
343 "kernel_load=0xa0000000\0" \
Prabhakar Kushwaha97421bd2015-07-01 16:28:22 +0530344 "kernel_size=0x28000000\0"
York Sun7288c2c2015-03-20 19:28:23 -0700345
Prabhakar Kushwahae60476a2015-03-20 19:28:26 -0700346#ifdef CONFIG_FSL_MC_ENET
347#define CONFIG_FSL_MEMAC
348#define CONFIG_PHYLIB
349#define CONFIG_PHYLIB_10G
350#define CONFIG_CMD_MII
351#define CONFIG_PHY_VITESSE
352#define CONFIG_PHY_REALTEK
353#define CONFIG_PHY_TERANETICS
354#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
355#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
356#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
357#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
358
359#define CONFIG_MII /* MII PHY management */
360#define CONFIG_ETHPRIME "DPNI1"
361#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
362
363#endif
364
York Sun7288c2c2015-03-20 19:28:23 -0700365#endif /* __LS2_QDS_H */