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Andy Fleming5f184712011-04-08 02:10:27 -05001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
Andy Flemingb21f87a32014-07-25 17:39:08 -05003 * Andy Fleming <afleming@gmail.com>
Andy Fleming5f184712011-04-08 02:10:27 -05004 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming5f184712011-04-08 02:10:27 -05006 *
7 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
8 */
9
10#ifndef _PHY_H
11#define _PHY_H
12
13#include <linux/list.h>
14#include <linux/mii.h>
15#include <linux/ethtool.h>
16#include <linux/mdio.h>
17
18#define PHY_MAX_ADDR 32
19
Shaohui Xieddcd1f32016-01-28 15:55:46 +080020#define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */
21
Florian Fainelli4dae6102016-01-13 16:59:33 +030022#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \
Andy Fleming5f184712011-04-08 02:10:27 -050023 SUPPORTED_TP | \
24 SUPPORTED_MII)
25
Florian Fainelli4dae6102016-01-13 16:59:33 +030026#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \
27 SUPPORTED_10baseT_Full)
28
29#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \
30 SUPPORTED_100baseT_Full)
31
32#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \
Andy Fleming5f184712011-04-08 02:10:27 -050033 SUPPORTED_1000baseT_Full)
34
Florian Fainelli4dae6102016-01-13 16:59:33 +030035#define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \
36 PHY_100BT_FEATURES | \
37 PHY_DEFAULT_FEATURES)
38
39#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \
40 PHY_1000BT_FEATURES)
41
Andy Fleming5f184712011-04-08 02:10:27 -050042#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
43 SUPPORTED_10000baseT_Full)
44
Stefan Roese4fb3f0c2014-10-22 12:13:15 +020045#ifndef PHY_ANEG_TIMEOUT
Andy Fleming5f184712011-04-08 02:10:27 -050046#define PHY_ANEG_TIMEOUT 4000
Stefan Roese4fb3f0c2014-10-22 12:13:15 +020047#endif
Andy Fleming5f184712011-04-08 02:10:27 -050048
49
50typedef enum {
51 PHY_INTERFACE_MODE_MII,
52 PHY_INTERFACE_MODE_GMII,
53 PHY_INTERFACE_MODE_SGMII,
Shengzhou Liuc35f8692014-10-23 17:20:57 +080054 PHY_INTERFACE_MODE_SGMII_2500,
Shaohui Xie7794b1a2013-03-25 07:39:31 +000055 PHY_INTERFACE_MODE_QSGMII,
Andy Fleming5f184712011-04-08 02:10:27 -050056 PHY_INTERFACE_MODE_TBI,
57 PHY_INTERFACE_MODE_RMII,
58 PHY_INTERFACE_MODE_RGMII,
59 PHY_INTERFACE_MODE_RGMII_ID,
60 PHY_INTERFACE_MODE_RGMII_RXID,
61 PHY_INTERFACE_MODE_RGMII_TXID,
62 PHY_INTERFACE_MODE_RTBI,
63 PHY_INTERFACE_MODE_XGMII,
Simon Glassc74c8e62015-04-05 16:07:39 -060064 PHY_INTERFACE_MODE_NONE, /* Must be last */
65
66 PHY_INTERFACE_MODE_COUNT,
Andy Fleming5f184712011-04-08 02:10:27 -050067} phy_interface_t;
68
69static const char *phy_interface_strings[] = {
70 [PHY_INTERFACE_MODE_MII] = "mii",
71 [PHY_INTERFACE_MODE_GMII] = "gmii",
72 [PHY_INTERFACE_MODE_SGMII] = "sgmii",
Shengzhou Liuc35f8692014-10-23 17:20:57 +080073 [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
Shaohui Xie7794b1a2013-03-25 07:39:31 +000074 [PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
Andy Fleming5f184712011-04-08 02:10:27 -050075 [PHY_INTERFACE_MODE_TBI] = "tbi",
76 [PHY_INTERFACE_MODE_RMII] = "rmii",
77 [PHY_INTERFACE_MODE_RGMII] = "rgmii",
78 [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
79 [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
80 [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
81 [PHY_INTERFACE_MODE_RTBI] = "rtbi",
82 [PHY_INTERFACE_MODE_XGMII] = "xgmii",
83 [PHY_INTERFACE_MODE_NONE] = "",
84};
85
86static inline const char *phy_string_for_interface(phy_interface_t i)
87{
88 /* Default to unknown */
89 if (i > PHY_INTERFACE_MODE_NONE)
90 i = PHY_INTERFACE_MODE_NONE;
91
92 return phy_interface_strings[i];
93}
94
95
96struct phy_device;
97
98#define MDIO_NAME_LEN 32
99
100struct mii_dev {
101 struct list_head link;
102 char name[MDIO_NAME_LEN];
103 void *priv;
104 int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
105 int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
106 u16 val);
107 int (*reset)(struct mii_dev *bus);
108 struct phy_device *phymap[PHY_MAX_ADDR];
109 u32 phy_mask;
110};
111
112/* struct phy_driver: a structure which defines PHY behavior
113 *
114 * uid will contain a number which represents the PHY. During
115 * startup, the driver will poll the PHY to find out what its
116 * UID--as defined by registers 2 and 3--is. The 32-bit result
117 * gotten from the PHY will be masked to
118 * discard any bits which may change based on revision numbers
119 * unimportant to functionality
120 *
121 */
122struct phy_driver {
123 char *name;
124 unsigned int uid;
125 unsigned int mask;
126 unsigned int mmds;
127
128 u32 features;
129
130 /* Called to do any driver startup necessities */
131 /* Will be called during phy_connect */
132 int (*probe)(struct phy_device *phydev);
133
134 /* Called to configure the PHY, and modify the controller
135 * based on the results. Should be called after phy_connect */
136 int (*config)(struct phy_device *phydev);
137
138 /* Called when starting up the controller */
139 int (*startup)(struct phy_device *phydev);
140
141 /* Called when bringing down the controller */
142 int (*shutdown)(struct phy_device *phydev);
143
Stefano Babicb71841b2013-09-02 15:42:30 +0200144 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
145 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
146 u16 val);
Andy Fleming5f184712011-04-08 02:10:27 -0500147 struct list_head list;
148};
149
150struct phy_device {
151 /* Information about the PHY type */
152 /* And management functions */
153 struct mii_dev *bus;
154 struct phy_driver *drv;
155 void *priv;
156
Simon Glassc74c8e62015-04-05 16:07:39 -0600157#ifdef CONFIG_DM_ETH
158 struct udevice *dev;
159#else
Andy Fleming5f184712011-04-08 02:10:27 -0500160 struct eth_device *dev;
Simon Glassc74c8e62015-04-05 16:07:39 -0600161#endif
Andy Fleming5f184712011-04-08 02:10:27 -0500162
163 /* forced speed & duplex (no autoneg)
164 * partner speed & duplex & pause (autoneg)
165 */
166 int speed;
167 int duplex;
168
169 /* The most recently read link state */
170 int link;
171 int port;
172 phy_interface_t interface;
173
174 u32 advertising;
175 u32 supported;
176 u32 mmds;
177
178 int autoneg;
179 int addr;
180 int pause;
181 int asym_pause;
182 u32 phy_id;
183 u32 flags;
184};
185
Shaohui Xief55a7762013-11-14 19:00:31 +0800186struct fixed_link {
187 int phy_id;
188 int duplex;
189 int link_speed;
190 int pause;
191 int asym_pause;
192};
193
Andy Fleming5f184712011-04-08 02:10:27 -0500194static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
195{
196 struct mii_dev *bus = phydev->bus;
197
198 return bus->read(bus, phydev->addr, devad, regnum);
199}
200
201static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
202 u16 val)
203{
204 struct mii_dev *bus = phydev->bus;
205
206 return bus->write(bus, phydev->addr, devad, regnum, val);
207}
208
209#ifdef CONFIG_PHYLIB_10G
210extern struct phy_driver gen10g_driver;
211
212/* For now, XGMII is the only 10G interface */
213static inline int is_10g_interface(phy_interface_t interface)
214{
215 return interface == PHY_INTERFACE_MODE_XGMII;
216}
217
218#endif
219
220int phy_init(void);
221int phy_reset(struct phy_device *phydev);
Troy Kisky1adb4062012-10-22 16:40:43 +0000222struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
223 phy_interface_t interface);
Simon Glassc74c8e62015-04-05 16:07:39 -0600224#ifdef CONFIG_DM_ETH
225void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
226struct phy_device *phy_connect(struct mii_dev *bus, int addr,
227 struct udevice *dev,
228 phy_interface_t interface);
229#else
Troy Kisky1adb4062012-10-22 16:40:43 +0000230void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
Andy Fleming5f184712011-04-08 02:10:27 -0500231struct phy_device *phy_connect(struct mii_dev *bus, int addr,
232 struct eth_device *dev,
233 phy_interface_t interface);
Simon Glassc74c8e62015-04-05 16:07:39 -0600234#endif
Andy Fleming5f184712011-04-08 02:10:27 -0500235int phy_startup(struct phy_device *phydev);
236int phy_config(struct phy_device *phydev);
237int phy_shutdown(struct phy_device *phydev);
238int phy_register(struct phy_driver *drv);
Alexey Brodkinb18acb02016-01-13 16:59:34 +0300239int phy_set_supported(struct phy_device *phydev, u32 max_speed);
Andy Fleming5f184712011-04-08 02:10:27 -0500240int genphy_config_aneg(struct phy_device *phydev);
Troy Kisky8682aba2012-02-07 14:08:48 +0000241int genphy_restart_aneg(struct phy_device *phydev);
Andy Fleming5f184712011-04-08 02:10:27 -0500242int genphy_update_link(struct phy_device *phydev);
Yegor Yefremove2043f52012-11-28 11:15:17 +0100243int genphy_parse_link(struct phy_device *phydev);
Andy Fleming5f184712011-04-08 02:10:27 -0500244int genphy_config(struct phy_device *phydev);
245int genphy_startup(struct phy_device *phydev);
246int genphy_shutdown(struct phy_device *phydev);
247int gen10g_config(struct phy_device *phydev);
248int gen10g_startup(struct phy_device *phydev);
249int gen10g_shutdown(struct phy_device *phydev);
250int gen10g_discover_mmds(struct phy_device *phydev);
251
Kevin Smith24ae3962016-03-31 19:33:12 +0000252int phy_mv88e61xx_init(void);
Shaohui Xief7c38cf2014-12-30 18:32:04 +0800253int phy_aquantia_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500254int phy_atheros_init(void);
255int phy_broadcom_init(void);
Shengzhou Liu9b18e512014-11-10 18:32:29 +0800256int phy_cortina_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500257int phy_davicom_init(void);
Matt Porterf485c8a2013-03-20 05:38:13 +0000258int phy_et1011c_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500259int phy_lxt_init(void);
260int phy_marvell_init(void);
261int phy_micrel_init(void);
262int phy_natsemi_init(void);
263int phy_realtek_init(void);
Vladimir Zapolskiyb6abf552011-12-29 15:18:37 +0000264int phy_smsc_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500265int phy_teranetics_init(void);
Edgar E. Iglesias721aed72015-09-25 23:46:08 -0700266int phy_ti_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500267int phy_vitesse_init(void);
Siva Durga Prasad Paladugued6fad32016-02-05 13:22:10 +0530268int phy_xilinx_init(void);
John Haechtena5fd13a2016-12-09 22:15:17 +0000269int phy_mscc_init(void);
Timur Tabia8366262011-10-18 18:44:34 -0500270
Fabio Estevam2fb63962014-02-15 14:52:00 -0200271int board_phy_config(struct phy_device *phydev);
Shengzhou Liu5707d5f2015-04-07 18:46:32 +0800272int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
Fabio Estevam2fb63962014-02-15 14:52:00 -0200273
Simon Glassc74c8e62015-04-05 16:07:39 -0600274/**
275 * phy_get_interface_by_name() - Look up a PHY interface name
276 *
277 * @str: PHY interface name, e.g. "mii"
278 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
279 */
280int phy_get_interface_by_name(const char *str);
281
Dan Murphy3ab72fe2016-05-02 15:46:00 -0500282/**
283 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
284 * is RGMII (all variants)
285 * @phydev: the phy_device struct
286 */
287static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
288{
289 return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
290 phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
291}
292
Dan Murphy3c221af2016-05-02 15:46:01 -0500293/**
294 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
295 * is SGMII (all variants)
296 * @phydev: the phy_device struct
297 */
298static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
299{
300 return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
301 phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
302}
303
Timur Tabia8366262011-10-18 18:44:34 -0500304/* PHY UIDs for various PHYs that are referenced in external code */
Shengzhou Liu9b18e512014-11-10 18:32:29 +0800305#define PHY_UID_CS4340 0x13e51002
Timur Tabia8366262011-10-18 18:44:34 -0500306#define PHY_UID_TN2020 0x00a19410
307
Andy Fleming5f184712011-04-08 02:10:27 -0500308#endif