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wdenk2262cfe2002-11-18 00:14:45 +00001/*
wdenk7a8e9bed2003-05-31 18:35:21 +00002 * (C) Copyright 2002, 2003
3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
wdenk8bde7f72003-06-27 21:31:46 +00004 *
wdenk2262cfe2002-11-18 00:14:45 +00005 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Alex Zuepke <azu@sysgo.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
wdenk7a8e9bed2003-05-31 18:35:21 +000029#include <asm/io.h>
30#include <pci.h>
31#include <asm/ic/sc520.h>
wdenk2262cfe2002-11-18 00:14:45 +000032
wdenk7a8e9bed2003-05-31 18:35:21 +000033#define PROBE_BUFFER_SIZE 1024
34static unsigned char buffer[PROBE_BUFFER_SIZE];
wdenk2262cfe2002-11-18 00:14:45 +000035
wdenk7a8e9bed2003-05-31 18:35:21 +000036#define SC520_MAX_FLASH_BANKS 3
37#define SC520_FLASH_BANK0_BASE 0x38000000 /* BOOTCS */
38#define SC520_FLASH_BANK1_BASE 0x30000000 /* ROMCS0 */
39#define SC520_FLASH_BANK2_BASE 0x28000000 /* ROMCS1 */
40#define SC520_FLASH_BANKSIZE 0x8000000
wdenk2262cfe2002-11-18 00:14:45 +000041
wdenk7a8e9bed2003-05-31 18:35:21 +000042#define AMD29LV016B_SIZE 0x200000
43#define AMD29LV016B_SECTORS 32
wdenk2262cfe2002-11-18 00:14:45 +000044
wdenk7a8e9bed2003-05-31 18:35:21 +000045flash_info_t flash_info[SC520_MAX_FLASH_BANKS];
wdenk2262cfe2002-11-18 00:14:45 +000046
47#define READY 1
48#define ERR 2
49#define TMO 4
50
51/*-----------------------------------------------------------------------
52 */
53
wdenk7a8e9bed2003-05-31 18:35:21 +000054
55static u32 _probe_flash(u32 addr, u32 bw, int il)
56{
57 u32 result=0;
wdenk8bde7f72003-06-27 21:31:46 +000058
wdenk7a8e9bed2003-05-31 18:35:21 +000059 /* First do an unlock cycle for the benefit of
60 * devices that need it */
wdenk8bde7f72003-06-27 21:31:46 +000061
wdenk7a8e9bed2003-05-31 18:35:21 +000062 switch (bw) {
wdenk8bde7f72003-06-27 21:31:46 +000063
wdenk7a8e9bed2003-05-31 18:35:21 +000064 case 1:
65 *(volatile u8*)(addr+0x5555) = 0xaa;
66 *(volatile u8*)(addr+0x2aaa) = 0x55;
67 *(volatile u8*)(addr+0x5555) = 0x90;
wdenk8bde7f72003-06-27 21:31:46 +000068
wdenk7a8e9bed2003-05-31 18:35:21 +000069 /* Read vendor */
70 result = *(volatile u8*)addr;
71 result <<= 16;
wdenk8bde7f72003-06-27 21:31:46 +000072
wdenk7a8e9bed2003-05-31 18:35:21 +000073 /* Read device */
74 result |= *(volatile u8*)(addr+2);
wdenk8bde7f72003-06-27 21:31:46 +000075
wdenk7a8e9bed2003-05-31 18:35:21 +000076 /* Return device to data mode */
77 *(volatile u8*)addr = 0xff;
wdenk8bde7f72003-06-27 21:31:46 +000078 *(volatile u8*)(addr+0x5555), 0xf0;
wdenk7a8e9bed2003-05-31 18:35:21 +000079 break;
wdenk8bde7f72003-06-27 21:31:46 +000080
wdenk7a8e9bed2003-05-31 18:35:21 +000081 case 2:
82 *(volatile u16*)(addr+0xaaaa) = 0xaaaa;
83 *(volatile u16*)(addr+0x5554) = 0x5555;
wdenk8bde7f72003-06-27 21:31:46 +000084
wdenk7a8e9bed2003-05-31 18:35:21 +000085 /* Issue identification command */
86 if (il == 2) {
87 *(volatile u16*)(addr+0xaaaa) = 0x9090;
wdenk8bde7f72003-06-27 21:31:46 +000088
wdenk7a8e9bed2003-05-31 18:35:21 +000089 /* Read vendor */
90 result = *(volatile u8*)addr;
91 result <<= 16;
wdenk8bde7f72003-06-27 21:31:46 +000092
wdenk7a8e9bed2003-05-31 18:35:21 +000093 /* Read device */
94 result |= *(volatile u8*)(addr+2);
wdenk8bde7f72003-06-27 21:31:46 +000095
wdenk7a8e9bed2003-05-31 18:35:21 +000096 /* Return device to data mode */
97 *(volatile u16*)addr = 0xffff;
wdenk8bde7f72003-06-27 21:31:46 +000098 *(volatile u16*)(addr+0xaaaa), 0xf0f0;
99
wdenk7a8e9bed2003-05-31 18:35:21 +0000100 } else {
101 *(volatile u8*)(addr+0xaaaa) = 0x90;
102 /* Read vendor */
103 result = *(volatile u16*)addr;
104 result <<= 16;
wdenk8bde7f72003-06-27 21:31:46 +0000105
wdenk7a8e9bed2003-05-31 18:35:21 +0000106 /* Read device */
107 result |= *(volatile u16*)(addr+2);
wdenk8bde7f72003-06-27 21:31:46 +0000108
wdenk7a8e9bed2003-05-31 18:35:21 +0000109 /* Return device to data mode */
110 *(volatile u8*)addr = 0xff;
wdenk8bde7f72003-06-27 21:31:46 +0000111 *(volatile u8*)(addr+0xaaaa), 0xf0;
wdenk7a8e9bed2003-05-31 18:35:21 +0000112 }
wdenk8bde7f72003-06-27 21:31:46 +0000113
wdenk7a8e9bed2003-05-31 18:35:21 +0000114 break;
wdenk8bde7f72003-06-27 21:31:46 +0000115
wdenk7a8e9bed2003-05-31 18:35:21 +0000116 case 4:
117 *(volatile u32*)(addr+0x5554) = 0xaaaaaaaa;
118 *(volatile u32*)(addr+0xaaa8) = 0x55555555;
wdenk8bde7f72003-06-27 21:31:46 +0000119
wdenk7a8e9bed2003-05-31 18:35:21 +0000120 switch (il) {
121 case 1:
122 /* Issue identification command */
123 *(volatile u8*)(addr+0x5554) = 0x90;
wdenk8bde7f72003-06-27 21:31:46 +0000124
wdenk7a8e9bed2003-05-31 18:35:21 +0000125 /* Read vendor */
126 result = *(volatile u16*)addr;
127 result <<= 16;
wdenk8bde7f72003-06-27 21:31:46 +0000128
wdenk7a8e9bed2003-05-31 18:35:21 +0000129 /* Read device */
130 result |= *(volatile u16*)(addr+4);
wdenk8bde7f72003-06-27 21:31:46 +0000131
wdenk7a8e9bed2003-05-31 18:35:21 +0000132 /* Return device to data mode */
133 *(volatile u8*)addr = 0xff;
wdenk8bde7f72003-06-27 21:31:46 +0000134 *(volatile u8*)(addr+0x5554), 0xf0;
wdenk7a8e9bed2003-05-31 18:35:21 +0000135 break;
wdenk8bde7f72003-06-27 21:31:46 +0000136
wdenk7a8e9bed2003-05-31 18:35:21 +0000137 case 2:
138 /* Issue identification command */
139 *(volatile u32*)(addr + 0x5554) = 0x00900090;
wdenk8bde7f72003-06-27 21:31:46 +0000140
wdenk7a8e9bed2003-05-31 18:35:21 +0000141 /* Read vendor */
142 result = *(volatile u16*)addr;
143 result <<= 16;
wdenk8bde7f72003-06-27 21:31:46 +0000144
wdenk7a8e9bed2003-05-31 18:35:21 +0000145 /* Read device */
146 result |= *(volatile u16*)(addr+4);
wdenk8bde7f72003-06-27 21:31:46 +0000147
wdenk7a8e9bed2003-05-31 18:35:21 +0000148 /* Return device to data mode */
149 *(volatile u32*)addr = 0x00ff00ff;
wdenk8bde7f72003-06-27 21:31:46 +0000150 *(volatile u32*)(addr+0x5554), 0x00f000f0;
wdenk7a8e9bed2003-05-31 18:35:21 +0000151 break;
wdenk8bde7f72003-06-27 21:31:46 +0000152
wdenk7a8e9bed2003-05-31 18:35:21 +0000153 case 4:
154 /* Issue identification command */
155 *(volatile u32*)(addr+0x5554) = 0x90909090;
wdenk8bde7f72003-06-27 21:31:46 +0000156
wdenk7a8e9bed2003-05-31 18:35:21 +0000157 /* Read vendor */
158 result = *(volatile u8*)addr;
159 result <<= 16;
wdenk8bde7f72003-06-27 21:31:46 +0000160
wdenk7a8e9bed2003-05-31 18:35:21 +0000161 /* Read device */
162 result |= *(volatile u8*)(addr+4);
wdenk8bde7f72003-06-27 21:31:46 +0000163
wdenk7a8e9bed2003-05-31 18:35:21 +0000164 /* Return device to data mode */
165 *(volatile u32*)addr = 0xffffffff;
wdenk8bde7f72003-06-27 21:31:46 +0000166 *(volatile u32*)(addr+0x5554), 0xf0f0f0f0;
wdenk7a8e9bed2003-05-31 18:35:21 +0000167 break;
168 }
169 break;
170 }
wdenk8bde7f72003-06-27 21:31:46 +0000171
172
wdenk7a8e9bed2003-05-31 18:35:21 +0000173 return result;
174}
175
176extern int _probe_flash_end;
177asm ("_probe_flash_end:\n"
178 ".long 0\n");
179
180static int identify_flash(unsigned address, int width)
181{
wdenk8bde7f72003-06-27 21:31:46 +0000182 int is;
wdenk7a8e9bed2003-05-31 18:35:21 +0000183 int device;
wdenk8bde7f72003-06-27 21:31:46 +0000184 int vendor;
wdenk7a8e9bed2003-05-31 18:35:21 +0000185 int size;
186 unsigned res;
wdenk8bde7f72003-06-27 21:31:46 +0000187
wdenk7a8e9bed2003-05-31 18:35:21 +0000188 u32 (*_probe_flash_ptr)(u32 a, u32 bw, int il);
wdenk8bde7f72003-06-27 21:31:46 +0000189
190 size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash;
191
wdenk7a8e9bed2003-05-31 18:35:21 +0000192 if (size > PROBE_BUFFER_SIZE) {
193 printf("_probe_flash() routine too large (%d) %p - %p\n",
194 size, &_probe_flash_end, _probe_flash);
195 return 0;
196 }
wdenk8bde7f72003-06-27 21:31:46 +0000197
wdenk7a8e9bed2003-05-31 18:35:21 +0000198 memcpy(buffer, _probe_flash, size);
199 _probe_flash_ptr = (void*)buffer;
wdenk8bde7f72003-06-27 21:31:46 +0000200
wdenk7a8e9bed2003-05-31 18:35:21 +0000201 is = disable_interrupts();
202 res = _probe_flash_ptr(address, width, 1);
203 if (is) {
204 enable_interrupts();
205 }
wdenk8bde7f72003-06-27 21:31:46 +0000206
207
208 vendor = res >> 16;
wdenk7a8e9bed2003-05-31 18:35:21 +0000209 device = res & 0xffff;
wdenk8bde7f72003-06-27 21:31:46 +0000210
211
wdenk7a8e9bed2003-05-31 18:35:21 +0000212 return res;
213}
214
wdenk2262cfe2002-11-18 00:14:45 +0000215ulong flash_init(void)
216{
wdenk7a8e9bed2003-05-31 18:35:21 +0000217 int i, j;
218 ulong size = 0;
wdenk8bde7f72003-06-27 21:31:46 +0000219
wdenk7a8e9bed2003-05-31 18:35:21 +0000220 for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) {
221 unsigned id;
222 ulong flashbase = 0;
wdenk8bde7f72003-06-27 21:31:46 +0000223 int sectsize = 0;
224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225 memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
wdenk7a8e9bed2003-05-31 18:35:21 +0000226 switch (i) {
227 case 0:
228 flashbase = SC520_FLASH_BANK0_BASE;
229 break;
230 case 1:
231 flashbase = SC520_FLASH_BANK1_BASE;
232 break;
233 case 2:
234 flashbase = SC520_FLASH_BANK2_BASE;
235 break;
236 default:
wdenk5f535fe2003-09-18 09:21:33 +0000237 panic("configured too many flash banks!\n");
wdenk2262cfe2002-11-18 00:14:45 +0000238 }
wdenk8bde7f72003-06-27 21:31:46 +0000239
wdenk7a8e9bed2003-05-31 18:35:21 +0000240 id = identify_flash(flashbase, 4);
241 switch (id & 0x00ff00ff) {
242 case 0x000100c8:
243 /* 29LV016B/29LV017B */
244 flash_info[i].flash_id =
245 (AMD_MANUFACT & FLASH_VENDMASK) |
246 (AMD_ID_LV016B & FLASH_TYPEMASK);
wdenk8bde7f72003-06-27 21:31:46 +0000247
wdenk7a8e9bed2003-05-31 18:35:21 +0000248 flash_info[i].size = AMD29LV016B_SIZE*4;
249 flash_info[i].sector_count = AMD29LV016B_SECTORS;
250 sectsize = (AMD29LV016B_SIZE*4)/AMD29LV016B_SECTORS;
251 printf("Bank %d: 4 x AMD 29LV017B\n", i);
252 break;
wdenk8bde7f72003-06-27 21:31:46 +0000253
254
wdenk7a8e9bed2003-05-31 18:35:21 +0000255 default:
256 printf("Bank %d have unknown flash %08x\n", i, id);
257 flash_info[i].flash_id = FLASH_UNKNOWN;
258 continue;
wdenk2262cfe2002-11-18 00:14:45 +0000259 }
wdenk8bde7f72003-06-27 21:31:46 +0000260
wdenk7a8e9bed2003-05-31 18:35:21 +0000261 for (j = 0; j < flash_info[i].sector_count; j++) {
262 flash_info[i].start[j] = flashbase + j * sectsize;
wdenk2262cfe2002-11-18 00:14:45 +0000263 }
wdenk7a8e9bed2003-05-31 18:35:21 +0000264 size += flash_info[i].size;
wdenk8bde7f72003-06-27 21:31:46 +0000265
wdenk7a8e9bed2003-05-31 18:35:21 +0000266 flash_protect(FLAG_PROTECT_CLEAR,
267 flash_info[i].start[0],
268 flash_info[i].start[0] + flash_info[i].size - 1,
269 &flash_info[i]);
wdenk2262cfe2002-11-18 00:14:45 +0000270 }
wdenk8bde7f72003-06-27 21:31:46 +0000271
wdenk7a8e9bed2003-05-31 18:35:21 +0000272 /*
273 * Protect monitor and environment sectors
274 */
275 flash_protect(FLAG_PROTECT_SET,
276 i386boot_start,
277 i386boot_end,
278 &flash_info[0]);
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200279#ifdef CONFIG_ENV_ADDR
wdenk7a8e9bed2003-05-31 18:35:21 +0000280 flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200281 CONFIG_ENV_ADDR,
282 CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
wdenk7a8e9bed2003-05-31 18:35:21 +0000283 &flash_info[0]);
wdenk8bde7f72003-06-27 21:31:46 +0000284#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000285 return size;
wdenk2262cfe2002-11-18 00:14:45 +0000286}
287
288/*-----------------------------------------------------------------------
289 */
wdenk7a8e9bed2003-05-31 18:35:21 +0000290void flash_print_info(flash_info_t *info)
wdenk2262cfe2002-11-18 00:14:45 +0000291{
wdenk7a8e9bed2003-05-31 18:35:21 +0000292 int i;
wdenk8bde7f72003-06-27 21:31:46 +0000293
wdenk7a8e9bed2003-05-31 18:35:21 +0000294 switch (info->flash_id & FLASH_VENDMASK) {
wdenk8bde7f72003-06-27 21:31:46 +0000295
wdenk7a8e9bed2003-05-31 18:35:21 +0000296 case (AMD_MANUFACT & FLASH_VENDMASK):
297 printf("AMD: ");
298 switch (info->flash_id & FLASH_TYPEMASK) {
299 case (AMD_ID_LV016B & FLASH_TYPEMASK):
300 printf("4x AMD29LV017B (4x16Mbit)\n");
301 break;
302 default:
303 printf("Unknown Chip Type\n");
304 goto done;
305 break;
306 }
wdenk8bde7f72003-06-27 21:31:46 +0000307
wdenk7a8e9bed2003-05-31 18:35:21 +0000308 break;
309 default:
310 printf("Unknown Vendor ");
311 break;
wdenk2262cfe2002-11-18 00:14:45 +0000312 }
wdenk8bde7f72003-06-27 21:31:46 +0000313
314
wdenk7a8e9bed2003-05-31 18:35:21 +0000315 printf(" Size: %ld MB in %d Sectors\n",
316 info->size >> 20, info->sector_count);
wdenk8bde7f72003-06-27 21:31:46 +0000317
wdenk7a8e9bed2003-05-31 18:35:21 +0000318 printf(" Sector Start Addresses:");
319 for (i = 0; i < info->sector_count; i++) {
320 if ((i % 5) == 0) {
321 printf ("\n ");
322 }
323 printf (" %08lX%s", info->start[i],
324 info->protect[i] ? " (RO)" : " ");
325 }
326 printf ("\n");
wdenk8bde7f72003-06-27 21:31:46 +0000327
wdenkbdccc4f2003-08-05 17:43:17 +0000328done: ;
wdenk2262cfe2002-11-18 00:14:45 +0000329}
330
331/*-----------------------------------------------------------------------
332 */
333
wdenk7a8e9bed2003-05-31 18:35:21 +0000334/* this needs to be inlined, the SWTMRMMILLI register is reset by each read */
335#define __udelay(delay) \
336{ \
337 unsigned micro; \
338 unsigned milli=0; \
339 \
340 micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
wdenk8bde7f72003-06-27 21:31:46 +0000341 \
wdenk7a8e9bed2003-05-31 18:35:21 +0000342 for (;;) { \
343 \
344 milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
345 micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \
346 \
347 if ((delay) <= (micro + (milli * 1000))) { \
348 break; \
349 } \
350 } \
wdenk8bde7f72003-06-27 21:31:46 +0000351} while (0)
wdenk7a8e9bed2003-05-31 18:35:21 +0000352
353static u32 _amd_erase_flash(u32 addr, u32 sector)
wdenk2262cfe2002-11-18 00:14:45 +0000354{
wdenk7a8e9bed2003-05-31 18:35:21 +0000355 unsigned elapsed;
wdenk8bde7f72003-06-27 21:31:46 +0000356
wdenk7a8e9bed2003-05-31 18:35:21 +0000357 /* Issue erase */
358 *(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA;
359 *(volatile u32*)(addr + 0xaaa8) = 0x55555555;
360 *(volatile u32*)(addr + 0x5554) = 0x80808080;
361 /* And one unlock */
362 *(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA;
363 *(volatile u32*)(addr + 0xaaa8) = 0x55555555;
364 /* Sector erase command comes last */
365 *(volatile u32*)(addr + sector) = 0x30303030;
wdenk8bde7f72003-06-27 21:31:46 +0000366
wdenk7a8e9bed2003-05-31 18:35:21 +0000367 elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
368 elapsed = 0;
369 __udelay(50);
370 while (((*(volatile u32*)(addr + sector)) & 0x80808080) != 0x80808080) {
wdenk8bde7f72003-06-27 21:31:46 +0000371
wdenk7a8e9bed2003-05-31 18:35:21 +0000372 elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373 if (elapsed > ((CONFIG_SYS_FLASH_ERASE_TOUT/CONFIG_SYS_HZ) * 1000)) {
wdenk7a8e9bed2003-05-31 18:35:21 +0000374 *(volatile u32*)(addr) = 0xf0f0f0f0;
wdenk8bde7f72003-06-27 21:31:46 +0000375 return 1;
wdenk2262cfe2002-11-18 00:14:45 +0000376 }
wdenk2262cfe2002-11-18 00:14:45 +0000377 }
wdenk8bde7f72003-06-27 21:31:46 +0000378
wdenk7a8e9bed2003-05-31 18:35:21 +0000379 *(volatile u32*)(addr) = 0xf0f0f0f0;
wdenk8bde7f72003-06-27 21:31:46 +0000380
wdenk7a8e9bed2003-05-31 18:35:21 +0000381 return 0;
382}
383
384extern int _amd_erase_flash_end;
385asm ("_amd_erase_flash_end:\n"
386 ".long 0\n");
387
388int flash_erase(flash_info_t *info, int s_first, int s_last)
389{
390 u32 (*_erase_flash_ptr)(u32 a, u32 so);
391 int prot;
392 int sect;
393 unsigned size;
wdenk8bde7f72003-06-27 21:31:46 +0000394
wdenk7a8e9bed2003-05-31 18:35:21 +0000395 if ((s_first < 0) || (s_first > s_last)) {
396 if (info->flash_id == FLASH_UNKNOWN) {
397 printf("- missing\n");
398 } else {
399 printf("- no sectors to erase\n");
400 }
401 return 1;
wdenk2262cfe2002-11-18 00:14:45 +0000402 }
wdenk8bde7f72003-06-27 21:31:46 +0000403
wdenk7a8e9bed2003-05-31 18:35:21 +0000404 if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) {
wdenk8bde7f72003-06-27 21:31:46 +0000405 size = (unsigned)&_amd_erase_flash_end - (unsigned)_amd_erase_flash;
406
wdenk7a8e9bed2003-05-31 18:35:21 +0000407 if (size > PROBE_BUFFER_SIZE) {
408 printf("_amd_erase_flash() routine too large (%d) %p - %p\n",
409 size, &_amd_erase_flash_end, _amd_erase_flash);
410 return 0;
411 }
wdenk8bde7f72003-06-27 21:31:46 +0000412
wdenk7a8e9bed2003-05-31 18:35:21 +0000413 memcpy(buffer, _amd_erase_flash, size);
414 _erase_flash_ptr = (void*)buffer;
wdenk8bde7f72003-06-27 21:31:46 +0000415
wdenk7a8e9bed2003-05-31 18:35:21 +0000416 } else {
417 printf ("Can't erase unknown flash type - aborted\n");
418 return 1;
419 }
wdenk8bde7f72003-06-27 21:31:46 +0000420
wdenk7a8e9bed2003-05-31 18:35:21 +0000421 prot = 0;
422 for (sect=s_first; sect<=s_last; ++sect) {
423 if (info->protect[sect]) {
424 prot++;
425 }
426 }
wdenk8bde7f72003-06-27 21:31:46 +0000427
wdenk7a8e9bed2003-05-31 18:35:21 +0000428 if (prot) {
429 printf ("- Warning: %d protected sectors will not be erased!\n", prot);
430 } else {
431 printf ("\n");
432 }
wdenk8bde7f72003-06-27 21:31:46 +0000433
434
wdenk7a8e9bed2003-05-31 18:35:21 +0000435 /* Start erase on unprotected sectors */
436 for (sect = s_first; sect<=s_last; sect++) {
wdenk8bde7f72003-06-27 21:31:46 +0000437
wdenk7a8e9bed2003-05-31 18:35:21 +0000438 if (info->protect[sect] == 0) { /* not protected */
439 int res;
440 int flag;
wdenk8bde7f72003-06-27 21:31:46 +0000441
wdenk7a8e9bed2003-05-31 18:35:21 +0000442 /* Disable interrupts which might cause a timeout here */
443 flag = disable_interrupts();
wdenk8bde7f72003-06-27 21:31:46 +0000444
wdenk7a8e9bed2003-05-31 18:35:21 +0000445 res = _erase_flash_ptr(info->start[0], info->start[sect]-info->start[0]);
wdenk8bde7f72003-06-27 21:31:46 +0000446
wdenk7a8e9bed2003-05-31 18:35:21 +0000447 /* re-enable interrupts if necessary */
448 if (flag) {
449 enable_interrupts();
450 }
wdenk8bde7f72003-06-27 21:31:46 +0000451
452
wdenk7a8e9bed2003-05-31 18:35:21 +0000453 if (res) {
454 printf("Erase timed out, sector %d\n", sect);
455 return res;
456 }
wdenk8bde7f72003-06-27 21:31:46 +0000457
458 putc('.');
459 }
wdenk7a8e9bed2003-05-31 18:35:21 +0000460 }
wdenk2262cfe2002-11-18 00:14:45 +0000461
wdenk8bde7f72003-06-27 21:31:46 +0000462
wdenk7a8e9bed2003-05-31 18:35:21 +0000463 return 0;
wdenk2262cfe2002-11-18 00:14:45 +0000464}
465
466/*-----------------------------------------------------------------------
wdenk7a8e9bed2003-05-31 18:35:21 +0000467 * Write a word to Flash, returns:
468 * 0 - OK
469 * 1 - write timeout
470 * 2 - Flash not erased
wdenk2262cfe2002-11-18 00:14:45 +0000471 */
wdenk7a8e9bed2003-05-31 18:35:21 +0000472static int _amd_write_word(unsigned start, unsigned dest, unsigned data)
wdenk2262cfe2002-11-18 00:14:45 +0000473{
wdenk7a8e9bed2003-05-31 18:35:21 +0000474 volatile u32 *addr2 = (u32*)start;
475 volatile u32 *dest2 = (u32*)dest;
476 volatile u32 *data2 = (u32*)&data;
477 unsigned elapsed;
wdenk8bde7f72003-06-27 21:31:46 +0000478
wdenk7a8e9bed2003-05-31 18:35:21 +0000479 /* Check if Flash is (sufficiently) erased */
480 if ((*((volatile u32*)dest) & (u32)data) != (u32)data) {
481 return 2;
wdenk2262cfe2002-11-18 00:14:45 +0000482 }
wdenk8bde7f72003-06-27 21:31:46 +0000483
wdenk7a8e9bed2003-05-31 18:35:21 +0000484 addr2[0x5554] = 0xAAAAAAAA;
485 addr2[0xaaa8] = 0x55555555;
486 addr2[0x5554] = 0xA0A0A0A0;
wdenk8bde7f72003-06-27 21:31:46 +0000487
wdenk7a8e9bed2003-05-31 18:35:21 +0000488 dest2[0] = data;
wdenk8bde7f72003-06-27 21:31:46 +0000489
wdenk7a8e9bed2003-05-31 18:35:21 +0000490 elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
491 elapsed = 0;
wdenk8bde7f72003-06-27 21:31:46 +0000492
wdenk7a8e9bed2003-05-31 18:35:21 +0000493 /* data polling for D7 */
494 while ((dest2[0] & 0x80808080) != (data2[0] & 0x80808080)) {
495 elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200496 if (elapsed > ((CONFIG_SYS_FLASH_WRITE_TOUT/CONFIG_SYS_HZ) * 1000)) {
wdenk7a8e9bed2003-05-31 18:35:21 +0000497 addr2[0] = 0xf0f0f0f0;
wdenk8bde7f72003-06-27 21:31:46 +0000498 return 1;
wdenk7a8e9bed2003-05-31 18:35:21 +0000499 }
wdenk2262cfe2002-11-18 00:14:45 +0000500 }
501
wdenk8bde7f72003-06-27 21:31:46 +0000502
wdenk7a8e9bed2003-05-31 18:35:21 +0000503 addr2[0] = 0xf0f0f0f0;
wdenk8bde7f72003-06-27 21:31:46 +0000504
wdenk7a8e9bed2003-05-31 18:35:21 +0000505 return 0;
wdenk2262cfe2002-11-18 00:14:45 +0000506}
507
wdenk7a8e9bed2003-05-31 18:35:21 +0000508extern int _amd_write_word_end;
509asm ("_amd_write_word_end:\n"
510 ".long 0\n");
511
512
wdenk2262cfe2002-11-18 00:14:45 +0000513/*-----------------------------------------------------------------------
wdenk7a8e9bed2003-05-31 18:35:21 +0000514 * Copy memory to flash, returns:
515 * 0 - OK
516 * 1 - write timeout
517 * 2 - Flash not erased
518 * 3 - Unsupported flash type
wdenk2262cfe2002-11-18 00:14:45 +0000519 */
520
wdenk7a8e9bed2003-05-31 18:35:21 +0000521int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
wdenk2262cfe2002-11-18 00:14:45 +0000522{
wdenk7a8e9bed2003-05-31 18:35:21 +0000523 ulong cp, wp, data;
524 int i, l, rc;
525 int flag;
526 u32 (*_write_word_ptr)(unsigned start, unsigned dest, unsigned data);
527 unsigned size;
wdenk8bde7f72003-06-27 21:31:46 +0000528
wdenk7a8e9bed2003-05-31 18:35:21 +0000529 if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) {
wdenk8bde7f72003-06-27 21:31:46 +0000530 size = (unsigned)&_amd_write_word_end - (unsigned)_amd_write_word;
531
wdenk7a8e9bed2003-05-31 18:35:21 +0000532 if (size > PROBE_BUFFER_SIZE) {
533 printf("_amd_write_word() routine too large (%d) %p - %p\n",
534 size, &_amd_write_word_end, _amd_write_word);
535 return 0;
536 }
wdenk8bde7f72003-06-27 21:31:46 +0000537
wdenk7a8e9bed2003-05-31 18:35:21 +0000538 memcpy(buffer, _amd_write_word, size);
539 _write_word_ptr = (void*)buffer;
wdenk8bde7f72003-06-27 21:31:46 +0000540
wdenk7a8e9bed2003-05-31 18:35:21 +0000541 } else {
542 printf ("Can't program unknown flash type - aborted\n");
543 return 3;
544 }
wdenk2262cfe2002-11-18 00:14:45 +0000545
wdenk2262cfe2002-11-18 00:14:45 +0000546
wdenk7a8e9bed2003-05-31 18:35:21 +0000547 wp = (addr & ~3); /* get lower word aligned address */
wdenk8bde7f72003-06-27 21:31:46 +0000548
wdenk7a8e9bed2003-05-31 18:35:21 +0000549
550 /*
551 * handle unaligned start bytes
552 */
553 if ((l = addr - wp) != 0) {
554 data = 0;
555 for (i=0, cp=wp; i<l; ++i, ++cp) {
556 data |= (*(uchar *)cp) << (8*i);
557 }
558 for (; i<4 && cnt>0; ++i) {
559 data |= *src++ << (8*i);
560 --cnt;
561 ++cp;
562 }
563 for (; cnt==0 && i<4; ++i, ++cp) {
564 data |= (*(uchar *)cp) << (8*i);
565 }
wdenk8bde7f72003-06-27 21:31:46 +0000566
wdenk7a8e9bed2003-05-31 18:35:21 +0000567 /* Disable interrupts which might cause a timeout here */
568 flag = disable_interrupts();
wdenk8bde7f72003-06-27 21:31:46 +0000569
wdenk7a8e9bed2003-05-31 18:35:21 +0000570 rc = _write_word_ptr(info->start[0], wp, data);
wdenk8bde7f72003-06-27 21:31:46 +0000571
wdenk7a8e9bed2003-05-31 18:35:21 +0000572 /* re-enable interrupts if necessary */
573 if (flag) {
574 enable_interrupts();
575 }
576 if (rc != 0) {
577 return rc;
578 }
579 wp += 4;
580 }
wdenk8bde7f72003-06-27 21:31:46 +0000581
wdenk7a8e9bed2003-05-31 18:35:21 +0000582 /*
583 * handle word aligned part
584 */
585 while (cnt >= 4) {
586 data = 0;
wdenk8bde7f72003-06-27 21:31:46 +0000587
wdenk7a8e9bed2003-05-31 18:35:21 +0000588 for (i=0; i<4; ++i) {
589 data |= *src++ << (8*i);
590 }
wdenk8bde7f72003-06-27 21:31:46 +0000591
wdenk7a8e9bed2003-05-31 18:35:21 +0000592 /* Disable interrupts which might cause a timeout here */
593 flag = disable_interrupts();
594
595 rc = _write_word_ptr(info->start[0], wp, data);
wdenk8bde7f72003-06-27 21:31:46 +0000596
wdenk7a8e9bed2003-05-31 18:35:21 +0000597 /* re-enable interrupts if necessary */
598 if (flag) {
599 enable_interrupts();
600 }
601 if (rc != 0) {
602 return rc;
603 }
604 wp += 4;
605 cnt -= 4;
606 }
wdenk8bde7f72003-06-27 21:31:46 +0000607
wdenk7a8e9bed2003-05-31 18:35:21 +0000608 if (cnt == 0) {
609 return 0;
610 }
wdenk8bde7f72003-06-27 21:31:46 +0000611
wdenk7a8e9bed2003-05-31 18:35:21 +0000612 /*
613 * handle unaligned tail bytes
614 */
wdenk2262cfe2002-11-18 00:14:45 +0000615 data = 0;
wdenk7a8e9bed2003-05-31 18:35:21 +0000616 for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
617 data |= *src++ << (8*i);
618 --cnt;
wdenk2262cfe2002-11-18 00:14:45 +0000619 }
wdenk8bde7f72003-06-27 21:31:46 +0000620
wdenk7a8e9bed2003-05-31 18:35:21 +0000621 for (; i<4; ++i, ++cp) {
622 data |= (*(uchar *)cp) << (8*i);
wdenk2262cfe2002-11-18 00:14:45 +0000623 }
624
wdenk7a8e9bed2003-05-31 18:35:21 +0000625 /* Disable interrupts which might cause a timeout here */
626 flag = disable_interrupts();
627
628 rc = _write_word_ptr(info->start[0], wp, data);
wdenk8bde7f72003-06-27 21:31:46 +0000629
wdenk7a8e9bed2003-05-31 18:35:21 +0000630 /* re-enable interrupts if necessary */
631 if (flag) {
632 enable_interrupts();
wdenk2262cfe2002-11-18 00:14:45 +0000633 }
wdenk8bde7f72003-06-27 21:31:46 +0000634
wdenk7a8e9bed2003-05-31 18:35:21 +0000635 return rc;
wdenk8bde7f72003-06-27 21:31:46 +0000636
wdenk2262cfe2002-11-18 00:14:45 +0000637}