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Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
Dave Liu03051c32007-09-18 12:36:11 +08002 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
Eran Libertyf046ccd2005-07-28 10:08:46 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
Eran Libertyf046ccd2005-07-28 10:08:46 -050011 */
12
Eran Libertyf046ccd2005-07-28 10:08:46 -050013#ifndef __MPC83XX_H__
14#define __MPC83XX_H__
15
Dave Liuf6eda7f2006-10-25 14:41:21 -050016#include <config.h>
Eran Libertyf046ccd2005-07-28 10:08:46 -050017#if defined(CONFIG_E300)
18#include <asm/e300.h>
19#endif
20
Dave Liue0803132006-12-07 21:11:58 +080021/* MPC83xx cpu provide RCR register to do reset thing specially
Eran Libertyf046ccd2005-07-28 10:08:46 -050022 */
Eran Libertyf046ccd2005-07-28 10:08:46 -050023#define MPC83xx_RESET
24
Dave Liue0803132006-12-07 21:11:58 +080025/* System reset offset (PowerPC standard)
Eran Libertyf046ccd2005-07-28 10:08:46 -050026 */
Dave Liue0803132006-12-07 21:11:58 +080027#define EXC_OFF_SYS_RESET 0x0100
Rafal Jaworowski02032e82007-06-22 14:58:04 +020028#define _START_OFFSET EXC_OFF_SYS_RESET
Eran Libertyf046ccd2005-07-28 10:08:46 -050029
Dave Liue0803132006-12-07 21:11:58 +080030/* IMMRBAR - Internal Memory Register Base Address
Eran Libertyf046ccd2005-07-28 10:08:46 -050031 */
Dave Liue0803132006-12-07 21:11:58 +080032#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */
33#define IMMRBAR 0x0000 /* Register offset to immr */
34#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */
35#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
Eran Libertyf046ccd2005-07-28 10:08:46 -050036
Dave Liue0803132006-12-07 21:11:58 +080037/* LAWBAR - Local Access Window Base Address Register
Eran Libertyf046ccd2005-07-28 10:08:46 -050038 */
Dave Liue0803132006-12-07 21:11:58 +080039#define LBLAWBAR0 0x0020 /* Register offset to immr */
40#define LBLAWAR0 0x0024
41#define LBLAWBAR1 0x0028
42#define LBLAWAR1 0x002C
43#define LBLAWBAR2 0x0030
44#define LBLAWAR2 0x0034
45#define LBLAWBAR3 0x0038
46#define LBLAWAR3 0x003C
47#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */
Eran Libertyf046ccd2005-07-28 10:08:46 -050048
Dave Liue0803132006-12-07 21:11:58 +080049/* SPRIDR - System Part and Revision ID Register
Eran Libertyf046ccd2005-07-28 10:08:46 -050050 */
Dave Liue0803132006-12-07 21:11:58 +080051#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */
52#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */
Eran Libertyf046ccd2005-07-28 10:08:46 -050053
Dave Liue0803132006-12-07 21:11:58 +080054#define SPR_8349E_REV10 0x80300100
55#define SPR_8349_REV10 0x80310100
56#define SPR_8347E_REV10_TBGA 0x80320100
57#define SPR_8347_REV10_TBGA 0x80330100
58#define SPR_8347E_REV10_PBGA 0x80340100
59#define SPR_8347_REV10_PBGA 0x80350100
60#define SPR_8343E_REV10 0x80360100
61#define SPR_8343_REV10 0x80370100
62
63#define SPR_8349E_REV11 0x80300101
64#define SPR_8349_REV11 0x80310101
65#define SPR_8347E_REV11_TBGA 0x80320101
66#define SPR_8347_REV11_TBGA 0x80330101
67#define SPR_8347E_REV11_PBGA 0x80340101
68#define SPR_8347_REV11_PBGA 0x80350101
69#define SPR_8343E_REV11 0x80360101
70#define SPR_8343_REV11 0x80370101
71
Xie Xiaobo8d172c02007-02-14 18:26:44 +080072#define SPR_8349E_REV31 0x80300300
73#define SPR_8349_REV31 0x80310300
74#define SPR_8347E_REV31_TBGA 0x80320300
75#define SPR_8347_REV31_TBGA 0x80330300
76#define SPR_8347E_REV31_PBGA 0x80340300
77#define SPR_8347_REV31_PBGA 0x80350300
78#define SPR_8343E_REV31 0x80360300
79#define SPR_8343_REV31 0x80370300
80
Dave Liue0803132006-12-07 21:11:58 +080081#define SPR_8360E_REV10 0x80480010
82#define SPR_8360_REV10 0x80490010
83#define SPR_8360E_REV11 0x80480011
84#define SPR_8360_REV11 0x80490011
85#define SPR_8360E_REV12 0x80480012
86#define SPR_8360_REV12 0x80490012
Xie Xiaobob110f402007-02-14 18:27:06 +080087#define SPR_8360E_REV20 0x80480020
88#define SPR_8360_REV20 0x80490020
Lee Nipper1ded0242007-06-14 20:07:33 -050089#define SPR_8360E_REV21 0x80480021
90#define SPR_8360_REV21 0x80490021
Dave Liue0803132006-12-07 21:11:58 +080091
Dave Liu24c3aca2006-12-07 21:13:15 +080092#define SPR_8323E_REV10 0x80620010
93#define SPR_8323_REV10 0x80630010
94#define SPR_8321E_REV10 0x80660010
95#define SPR_8321_REV10 0x80670010
96#define SPR_8323E_REV11 0x80620011
97#define SPR_8323_REV11 0x80630011
98#define SPR_8321E_REV11 0x80660011
99#define SPR_8321_REV11 0x80670011
100
Scott Woodd87c57b2007-04-16 14:31:55 -0500101#define SPR_8313E_REV10 0x80B00010
Dave Liu03051c32007-09-18 12:36:11 +0800102#define SPR_8313_REV10 0x80B10010
103#define SPR_8311E_REV10 0x80B20010
104#define SPR_8311_REV10 0x80B30010
Dave Liu555da612007-09-18 12:36:58 +0800105#define SPR_8315E_REV10 0x80B40010
106#define SPR_8315_REV10 0x80B50010
107#define SPR_8314E_REV10 0x80B60010
108#define SPR_8314_REV10 0x80B70010
Dave Liu03051c32007-09-18 12:36:11 +0800109
110#define SPR_8379E_REV10 0x80C20010
111#define SPR_8379_REV10 0x80C30010
112#define SPR_8378E_REV10 0x80C40010
113#define SPR_8378_REV10 0x80C50010
114#define SPR_8377E_REV10 0x80C60010
115#define SPR_8377_REV10 0x80C70010
Scott Woodd87c57b2007-04-16 14:31:55 -0500116
Dave Liue0803132006-12-07 21:11:58 +0800117/* SPCR - System Priority Configuration Register
Eran Libertyf046ccd2005-07-28 10:08:46 -0500118 */
Dave Liue0803132006-12-07 21:11:58 +0800119#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */
120#define SPCR_PCIHPE_SHIFT (31-3)
121#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */
122#define SPCR_PCIPR_SHIFT (31-7)
123#define SPCR_OPT 0x00800000 /* Optimize */
124#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */
125#define SPCR_TBEN_SHIFT (31-9)
126#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */
127#define SPCR_COREPR_SHIFT (31-11)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500128
Kumar Gala3e78a312007-01-30 14:08:30 -0600129#if defined(CONFIG_MPC834X)
Dave Liue0803132006-12-07 21:11:58 +0800130/* SPCR bits - MPC8349 specific */
131#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */
132#define SPCR_TSEC1DP_SHIFT (31-19)
133#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */
134#define SPCR_TSEC1BDP_SHIFT (31-21)
135#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */
136#define SPCR_TSEC1EP_SHIFT (31-23)
137#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */
138#define SPCR_TSEC2DP_SHIFT (31-27)
139#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */
140#define SPCR_TSEC2BDP_SHIFT (31-29)
141#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */
142#define SPCR_TSEC2EP_SHIFT (31-31)
Scott Woodd87c57b2007-04-16 14:31:55 -0500143
Dave Liu03051c32007-09-18 12:36:11 +0800144#elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
145/* SPCR bits - MPC831x and MPC837x specific */
Scott Woodd87c57b2007-04-16 14:31:55 -0500146#define SPCR_TSECDP 0x00003000 /* TSEC data priority */
147#define SPCR_TSECDP_SHIFT (31-19)
Dave Liuec2638e2008-01-10 23:05:00 +0800148#define SPCR_TSECBDP 0x00000C00 /* TSEC buffer descriptor priority */
149#define SPCR_TSECBDP_SHIFT (31-21)
150#define SPCR_TSECEP 0x00000300 /* TSEC emergency priority */
151#define SPCR_TSECEP_SHIFT (31-23)
Dave Liu5f820432006-11-03 19:33:44 -0600152#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500153
Dave Liue0803132006-12-07 21:11:58 +0800154/* SICRL/H - System I/O Configuration Register Low/High
155 */
Kumar Gala3e78a312007-01-30 14:08:30 -0600156#if defined(CONFIG_MPC834X)
Dave Liue0803132006-12-07 21:11:58 +0800157/* SICRL bits - MPC8349 specific */
158#define SICRL_LDP_A 0x80000000
159#define SICRL_USB1 0x40000000
160#define SICRL_USB0 0x20000000
161#define SICRL_UART 0x0C000000
162#define SICRL_GPIO1_A 0x02000000
163#define SICRL_GPIO1_B 0x01000000
164#define SICRL_GPIO1_C 0x00800000
165#define SICRL_GPIO1_D 0x00400000
166#define SICRL_GPIO1_E 0x00200000
167#define SICRL_GPIO1_F 0x00180000
168#define SICRL_GPIO1_G 0x00040000
169#define SICRL_GPIO1_H 0x00020000
170#define SICRL_GPIO1_I 0x00010000
171#define SICRL_GPIO1_J 0x00008000
172#define SICRL_GPIO1_K 0x00004000
173#define SICRL_GPIO1_L 0x00003000
Eran Libertyf046ccd2005-07-28 10:08:46 -0500174
Dave Liue0803132006-12-07 21:11:58 +0800175/* SICRH bits - MPC8349 specific */
176#define SICRH_DDR 0x80000000
177#define SICRH_TSEC1_A 0x10000000
178#define SICRH_TSEC1_B 0x08000000
179#define SICRH_TSEC1_C 0x04000000
180#define SICRH_TSEC1_D 0x02000000
181#define SICRH_TSEC1_E 0x01000000
182#define SICRH_TSEC1_F 0x00800000
183#define SICRH_TSEC2_A 0x00400000
184#define SICRH_TSEC2_B 0x00200000
185#define SICRH_TSEC2_C 0x00100000
186#define SICRH_TSEC2_D 0x00080000
187#define SICRH_TSEC2_E 0x00040000
188#define SICRH_TSEC2_F 0x00020000
189#define SICRH_TSEC2_G 0x00010000
190#define SICRH_TSEC2_H 0x00008000
191#define SICRH_GPIO2_A 0x00004000
192#define SICRH_GPIO2_B 0x00002000
193#define SICRH_GPIO2_C 0x00001000
194#define SICRH_GPIO2_D 0x00000800
195#define SICRH_GPIO2_E 0x00000400
196#define SICRH_GPIO2_F 0x00000200
197#define SICRH_GPIO2_G 0x00000180
198#define SICRH_GPIO2_H 0x00000060
199#define SICRH_TSOBI1 0x00000002
200#define SICRH_TSOBI2 0x00000001
201
202#elif defined(CONFIG_MPC8360)
203/* SICRL bits - MPC8360 specific */
204#define SICRL_LDP_A 0xC0000000
205#define SICRL_LCLK_1 0x10000000
206#define SICRL_LCLK_2 0x08000000
207#define SICRL_SRCID_A 0x03000000
208#define SICRL_IRQ_CKSTP_A 0x00C00000
209
210/* SICRH bits - MPC8360 specific */
211#define SICRH_DDR 0x80000000
212#define SICRH_SECONDARY_DDR 0x40000000
213#define SICRH_SDDROE 0x20000000
214#define SICRH_IRQ3 0x10000000
215#define SICRH_UC1EOBI 0x00000004
216#define SICRH_UC2E1OBI 0x00000002
217#define SICRH_UC2E2OBI 0x00000001
Dave Liu24c3aca2006-12-07 21:13:15 +0800218
219#elif defined(CONFIG_MPC832X)
220/* SICRL bits - MPC832X specific */
221#define SICRL_LDP_LCS_A 0x80000000
222#define SICRL_IRQ_CKS 0x20000000
223#define SICRL_PCI_MSRC 0x10000000
224#define SICRL_URT_CTPR 0x06000000
225#define SICRL_IRQ_CTPR 0x00C00000
Scott Woodd87c57b2007-04-16 14:31:55 -0500226
Dave Liu555da612007-09-18 12:36:58 +0800227#elif defined(CONFIG_MPC8313)
228/* SICRL bits - MPC8313 specific */
Scott Woodd87c57b2007-04-16 14:31:55 -0500229#define SICRL_LBC 0x30000000
230#define SICRL_UART 0x0C000000
231#define SICRL_SPI_A 0x03000000
232#define SICRL_SPI_B 0x00C00000
233#define SICRL_SPI_C 0x00300000
234#define SICRL_SPI_D 0x000C0000
235#define SICRL_USBDR 0x00000C00
236#define SICRL_ETSEC1_A 0x0000000C
237#define SICRL_ETSEC2_A 0x00000003
238
Dave Liu555da612007-09-18 12:36:58 +0800239/* SICRH bits - MPC8313 specific */
Scott Woodd87c57b2007-04-16 14:31:55 -0500240#define SICRH_INTR_A 0x02000000
241#define SICRH_INTR_B 0x00C00000
242#define SICRH_IIC 0x00300000
243#define SICRH_ETSEC2_B 0x000C0000
244#define SICRH_ETSEC2_C 0x00030000
245#define SICRH_ETSEC2_D 0x0000C000
246#define SICRH_ETSEC2_E 0x00003000
247#define SICRH_ETSEC2_F 0x00000C00
248#define SICRH_ETSEC2_G 0x00000300
249#define SICRH_ETSEC1_B 0x00000080
250#define SICRH_ETSEC1_C 0x00000060
251#define SICRH_GTX1_DLY 0x00000008
252#define SICRH_GTX2_DLY 0x00000004
253#define SICRH_TSOBI1 0x00000002
254#define SICRH_TSOBI2 0x00000001
255
Dave Liu555da612007-09-18 12:36:58 +0800256#elif defined(CONFIG_MPC8315)
257/* SICRL bits - MPC8315 specific */
258#define SICRL_DMA_CH0 0xc0000000
259#define SICRL_DMA_SPI 0x30000000
260#define SICRL_UART 0x0c000000
261#define SICRL_IRQ4 0x02000000
262#define SICRL_IRQ5 0x01800000
263#define SICRL_IRQ6_7 0x00400000
264#define SICRL_IIC1 0x00300000
265#define SICRL_TDM 0x000c0000
266#define SICRL_TDM_SHARED 0x00030000
267#define SICRL_PCI_A 0x0000c000
268#define SICRL_ELBC_A 0x00003000
269#define SICRL_ETSEC1_A 0x000000c0
270#define SICRL_ETSEC1_B 0x00000030
271#define SICRL_ETSEC1_C 0x0000000c
272#define SICRL_TSEXPOBI 0x00000001
273
274/* SICRH bits - MPC8315 specific */
275#define SICRH_GPIO_0 0xc0000000
276#define SICRH_GPIO_1 0x30000000
277#define SICRH_GPIO_2 0x0c000000
278#define SICRH_GPIO_3 0x03000000
279#define SICRH_GPIO_4 0x00c00000
280#define SICRH_GPIO_5 0x00300000
281#define SICRH_GPIO_6 0x000c0000
282#define SICRH_GPIO_7 0x00030000
283#define SICRH_GPIO_8 0x0000c000
284#define SICRH_GPIO_9 0x00003000
285#define SICRH_GPIO_10 0x00000c00
286#define SICRH_GPIO_11 0x00000300
287#define SICRH_ETSEC2_A 0x000000c0
288#define SICRH_TSOBI1 0x00000002
289#define SICRH_TSOBI2 0x00000001
290
Dave Liu03051c32007-09-18 12:36:11 +0800291#elif defined(CONFIG_MPC837X)
292/* SICRL bits - MPC837x specific */
293#define SICRL_USB_A 0xC0000000
294#define SICRL_USB_B 0x30000000
295#define SICRL_UART 0x0C000000
296#define SICRL_GPIO_A 0x02000000
297#define SICRL_GPIO_B 0x01000000
298#define SICRL_GPIO_C 0x00800000
299#define SICRL_GPIO_D 0x00400000
300#define SICRL_GPIO_E 0x00200000
301#define SICRL_GPIO_F 0x00180000
302#define SICRL_GPIO_G 0x00040000
303#define SICRL_GPIO_H 0x00020000
304#define SICRL_GPIO_I 0x00010000
305#define SICRL_GPIO_J 0x00008000
306#define SICRL_GPIO_K 0x00004000
307#define SICRL_GPIO_L 0x00003000
308#define SICRL_DMA_A 0x00000800
309#define SICRL_DMA_B 0x00000400
310#define SICRL_DMA_C 0x00000200
311#define SICRL_DMA_D 0x00000100
312#define SICRL_DMA_E 0x00000080
313#define SICRL_DMA_F 0x00000040
314#define SICRL_DMA_G 0x00000020
315#define SICRL_DMA_H 0x00000010
316#define SICRL_DMA_I 0x00000008
317#define SICRL_DMA_J 0x00000004
318#define SICRL_LDP_A 0x00000002
319#define SICRL_LDP_B 0x00000001
320
321/* SICRH bits - MPC837x specific */
322#define SICRH_DDR 0x80000000
323#define SICRH_TSEC1_A 0x10000000
324#define SICRH_TSEC1_B 0x08000000
325#define SICRH_TSEC2_A 0x00400000
326#define SICRH_TSEC2_B 0x00200000
327#define SICRH_TSEC2_C 0x00100000
328#define SICRH_TSEC2_D 0x00080000
329#define SICRH_TSEC2_E 0x00040000
330#define SICRH_TMR 0x00010000
331#define SICRH_GPIO2_A 0x00008000
332#define SICRH_GPIO2_B 0x00004000
333#define SICRH_GPIO2_C 0x00002000
334#define SICRH_GPIO2_D 0x00001000
335#define SICRH_GPIO2_E 0x00000C00
336#define SICRH_GPIO2_F 0x00000300
337#define SICRH_GPIO2_G 0x000000C0
338#define SICRH_GPIO2_H 0x00000030
339#define SICRH_SPI 0x00000003
Dave Liue0803132006-12-07 21:11:58 +0800340#endif
341
342/* SWCRR - System Watchdog Control Register
343 */
344#define SWCRR 0x0204 /* Register offset to immr */
345#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */
346#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */
347#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */
348#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */
349#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
350
351/* SWCNR - System Watchdog Counter Register
352 */
353#define SWCNR 0x0208 /* Register offset to immr */
354#define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */
355#define SWCNR_RES ~(SWCNR_SWCN)
356
357/* SWSRR - System Watchdog Service Register
358 */
359#define SWSRR 0x020E /* Register offset to immr */
360
361/* ACR - Arbiter Configuration Register
362 */
363#define ACR_COREDIS 0x10000000 /* Core disable */
364#define ACR_COREDIS_SHIFT (31-7)
365#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
366#define ACR_PIPE_DEP_SHIFT (31-15)
367#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
368#define ACR_PCI_RPTCNT_SHIFT (31-19)
369#define ACR_RPTCNT 0x00000700 /* Repeat count */
370#define ACR_RPTCNT_SHIFT (31-23)
371#define ACR_APARK 0x00000030 /* Address parking */
372#define ACR_APARK_SHIFT (31-27)
373#define ACR_PARKM 0x0000000F /* Parking master */
374#define ACR_PARKM_SHIFT (31-31)
375
376/* ATR - Arbiter Timers Register
377 */
378#define ATR_DTO 0x00FF0000 /* Data time out */
379#define ATR_ATO 0x000000FF /* Address time out */
380
381/* AER - Arbiter Event Register
382 */
383#define AER_ETEA 0x00000020 /* Transfer error */
384#define AER_RES 0x00000010 /* Reserved transfer type */
385#define AER_ECW 0x00000008 /* External control word transfer type */
386#define AER_AO 0x00000004 /* Address Only transfer type */
387#define AER_DTO 0x00000002 /* Data time out */
388#define AER_ATO 0x00000001 /* Address time out */
389
390/* AEATR - Arbiter Event Address Register
391 */
392#define AEATR_EVENT 0x07000000 /* Event type */
393#define AEATR_MSTR_ID 0x001F0000 /* Master Id */
394#define AEATR_TBST 0x00000800 /* Transfer burst */
395#define AEATR_TSIZE 0x00000700 /* Transfer Size */
396#define AEATR_TTYPE 0x0000001F /* Transfer Type */
397
398/* HRCWL - Hard Reset Configuration Word Low
399 */
400#define HRCWL_LBIUCM 0x80000000
401#define HRCWL_LBIUCM_SHIFT 31
402#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
403#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
404
405#define HRCWL_DDRCM 0x40000000
406#define HRCWL_DDRCM_SHIFT 30
407#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000
408#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000
409
410#define HRCWL_SPMF 0x0f000000
411#define HRCWL_SPMF_SHIFT 24
412#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000
413#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000
414#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000
415#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000
416#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000
417#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000
418#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000
419#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000
420#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000
421#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000
422#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000
423#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000
424#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000
425#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000
426#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000
427#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000
428
429#define HRCWL_VCO_BYPASS 0x00000000
430#define HRCWL_VCO_1X2 0x00000000
431#define HRCWL_VCO_1X4 0x00200000
432#define HRCWL_VCO_1X8 0x00400000
433
434#define HRCWL_COREPLL 0x007F0000
435#define HRCWL_COREPLL_SHIFT 16
436#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000
437#define HRCWL_CORE_TO_CSB_1X1 0x00020000
438#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000
439#define HRCWL_CORE_TO_CSB_2X1 0x00040000
440#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
441#define HRCWL_CORE_TO_CSB_3X1 0x00060000
442
Dave Liu24c3aca2006-12-07 21:13:15 +0800443#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
Dave Liue0803132006-12-07 21:11:58 +0800444#define HRCWL_CEVCOD 0x000000C0
445#define HRCWL_CEVCOD_SHIFT 6
446#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
447#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040
448#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080
449
450#define HRCWL_CEPDF 0x00000020
451#define HRCWL_CEPDF_SHIFT 5
452#define HRCWL_CE_PLL_DIV_1X1 0x00000000
453#define HRCWL_CE_PLL_DIV_2X1 0x00000020
454
455#define HRCWL_CEPMF 0x0000001F
456#define HRCWL_CEPMF_SHIFT 0
457#define HRCWL_CE_TO_PLL_1X16_ 0x00000000
458#define HRCWL_CE_TO_PLL_1X2 0x00000002
459#define HRCWL_CE_TO_PLL_1X3 0x00000003
460#define HRCWL_CE_TO_PLL_1X4 0x00000004
461#define HRCWL_CE_TO_PLL_1X5 0x00000005
462#define HRCWL_CE_TO_PLL_1X6 0x00000006
463#define HRCWL_CE_TO_PLL_1X7 0x00000007
464#define HRCWL_CE_TO_PLL_1X8 0x00000008
465#define HRCWL_CE_TO_PLL_1X9 0x00000009
466#define HRCWL_CE_TO_PLL_1X10 0x0000000A
467#define HRCWL_CE_TO_PLL_1X11 0x0000000B
468#define HRCWL_CE_TO_PLL_1X12 0x0000000C
469#define HRCWL_CE_TO_PLL_1X13 0x0000000D
470#define HRCWL_CE_TO_PLL_1X14 0x0000000E
471#define HRCWL_CE_TO_PLL_1X15 0x0000000F
472#define HRCWL_CE_TO_PLL_1X16 0x00000010
473#define HRCWL_CE_TO_PLL_1X17 0x00000011
474#define HRCWL_CE_TO_PLL_1X18 0x00000012
475#define HRCWL_CE_TO_PLL_1X19 0x00000013
476#define HRCWL_CE_TO_PLL_1X20 0x00000014
477#define HRCWL_CE_TO_PLL_1X21 0x00000015
478#define HRCWL_CE_TO_PLL_1X22 0x00000016
479#define HRCWL_CE_TO_PLL_1X23 0x00000017
480#define HRCWL_CE_TO_PLL_1X24 0x00000018
481#define HRCWL_CE_TO_PLL_1X25 0x00000019
482#define HRCWL_CE_TO_PLL_1X26 0x0000001A
483#define HRCWL_CE_TO_PLL_1X27 0x0000001B
484#define HRCWL_CE_TO_PLL_1X28 0x0000001C
485#define HRCWL_CE_TO_PLL_1X29 0x0000001D
486#define HRCWL_CE_TO_PLL_1X30 0x0000001E
487#define HRCWL_CE_TO_PLL_1X31 0x0000001F
Dave Liu03051c32007-09-18 12:36:11 +0800488
Dave Liu6f3931a2008-01-10 23:06:05 +0800489#elif defined(CONFIG_MPC8315)
490#define HRCWL_SVCOD 0x30000000
491#define HRCWL_SVCOD_SHIFT 28
492#define HRCWL_SVCOD_DIV_2 0x00000000
493#define HRCWL_SVCOD_DIV_4 0x10000000
494#define HRCWL_SVCOD_DIV_8 0x20000000
495#define HRCWL_SVCOD_DIV_1 0x30000000
496
497#elif defined(CONFIG_MPC837X)
Dave Liu03051c32007-09-18 12:36:11 +0800498#define HRCWL_SVCOD 0x30000000
499#define HRCWL_SVCOD_SHIFT 28
500#define HRCWL_SVCOD_DIV_4 0x00000000
501#define HRCWL_SVCOD_DIV_8 0x10000000
502#define HRCWL_SVCOD_DIV_2 0x20000000
503#define HRCWL_SVCOD_DIV_1 0x30000000
Dave Liue0803132006-12-07 21:11:58 +0800504#endif
505
506/* HRCWH - Hardware Reset Configuration Word High
507 */
508#define HRCWH_PCI_HOST 0x80000000
509#define HRCWH_PCI_HOST_SHIFT 31
510#define HRCWH_PCI_AGENT 0x00000000
511
Kumar Gala3e78a312007-01-30 14:08:30 -0600512#if defined(CONFIG_MPC834X)
Dave Liue0803132006-12-07 21:11:58 +0800513#define HRCWH_32_BIT_PCI 0x00000000
514#define HRCWH_64_BIT_PCI 0x40000000
515#endif
516
517#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
518#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
519
520#define HRCWH_PCI_ARBITER_DISABLE 0x00000000
521#define HRCWH_PCI_ARBITER_ENABLE 0x20000000
522
Kumar Gala3e78a312007-01-30 14:08:30 -0600523#if defined(CONFIG_MPC834X)
Dave Liue0803132006-12-07 21:11:58 +0800524#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
525#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
526
527#elif defined(CONFIG_MPC8360)
528#define HRCWH_PCICKDRV_DISABLE 0x00000000
529#define HRCWH_PCICKDRV_ENABLE 0x10000000
530#endif
531
532#define HRCWH_CORE_DISABLE 0x08000000
533#define HRCWH_CORE_ENABLE 0x00000000
534
535#define HRCWH_FROM_0X00000100 0x00000000
536#define HRCWH_FROM_0XFFF00100 0x04000000
537
538#define HRCWH_BOOTSEQ_DISABLE 0x00000000
539#define HRCWH_BOOTSEQ_NORMAL 0x01000000
540#define HRCWH_BOOTSEQ_EXTENDED 0x02000000
541
542#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
543#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
544
545#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
546#define HRCWH_ROM_LOC_PCI1 0x00100000
Kumar Gala3e78a312007-01-30 14:08:30 -0600547#if defined(CONFIG_MPC834X)
Dave Liue0803132006-12-07 21:11:58 +0800548#define HRCWH_ROM_LOC_PCI2 0x00200000
549#endif
Dave Liu03051c32007-09-18 12:36:11 +0800550#if defined(CONIFG_MPC837X)
551#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
552#endif
Dave Liue0803132006-12-07 21:11:58 +0800553#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
554#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
555#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
556
Dave Liu03051c32007-09-18 12:36:11 +0800557#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200558#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
Scott Woodd87c57b2007-04-16 14:31:55 -0500559#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200560#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
Scott Woodd87c57b2007-04-16 14:31:55 -0500561#define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000
562
563#define HRCWH_RL_EXT_LEGACY 0x00000000
564#define HRCWH_RL_EXT_NAND 0x00040000
565
566#define HRCWH_TSEC1M_IN_MII 0x00000000
567#define HRCWH_TSEC1M_IN_RMII 0x00002000
568#define HRCWH_TSEC1M_IN_RGMII 0x00006000
569#define HRCWH_TSEC1M_IN_RTBI 0x0000A000
570#define HRCWH_TSEC1M_IN_SGMII 0x0000C000
571
572#define HRCWH_TSEC2M_IN_MII 0x00000000
573#define HRCWH_TSEC2M_IN_RMII 0x00000400
574#define HRCWH_TSEC2M_IN_RGMII 0x00000C00
575#define HRCWH_TSEC2M_IN_RTBI 0x00001400
576#define HRCWH_TSEC2M_IN_SGMII 0x00001800
577#endif
578
Kumar Gala3e78a312007-01-30 14:08:30 -0600579#if defined(CONFIG_MPC834X)
Dave Liue0803132006-12-07 21:11:58 +0800580#define HRCWH_TSEC1M_IN_RGMII 0x00000000
581#define HRCWH_TSEC1M_IN_RTBI 0x00004000
582#define HRCWH_TSEC1M_IN_GMII 0x00008000
583#define HRCWH_TSEC1M_IN_TBI 0x0000C000
584#define HRCWH_TSEC2M_IN_RGMII 0x00000000
585#define HRCWH_TSEC2M_IN_RTBI 0x00001000
586#define HRCWH_TSEC2M_IN_GMII 0x00002000
587#define HRCWH_TSEC2M_IN_TBI 0x00003000
588#endif
589
590#if defined(CONFIG_MPC8360)
591#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
592#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
593#endif
594
595#define HRCWH_BIG_ENDIAN 0x00000000
596#define HRCWH_LITTLE_ENDIAN 0x00000008
597
598#define HRCWH_LALE_NORMAL 0x00000000
599#define HRCWH_LALE_EARLY 0x00000004
600
601#define HRCWH_LDP_SET 0x00000000
602#define HRCWH_LDP_CLEAR 0x00000002
603
604/* RSR - Reset Status Register
605 */
Dave Liu555da612007-09-18 12:36:58 +0800606#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
Dave Liu03051c32007-09-18 12:36:11 +0800607#define RSR_RSTSRC 0xF0000000 /* Reset source */
608#define RSR_RSTSRC_SHIFT 28
609#else
Dave Liue0803132006-12-07 21:11:58 +0800610#define RSR_RSTSRC 0xE0000000 /* Reset source */
611#define RSR_RSTSRC_SHIFT 29
Dave Liu03051c32007-09-18 12:36:11 +0800612#endif
Dave Liue0803132006-12-07 21:11:58 +0800613#define RSR_BSF 0x00010000 /* Boot seq. fail */
614#define RSR_BSF_SHIFT 16
615#define RSR_SWSR 0x00002000 /* software soft reset */
616#define RSR_SWSR_SHIFT 13
617#define RSR_SWHR 0x00001000 /* software hard reset */
618#define RSR_SWHR_SHIFT 12
619#define RSR_JHRS 0x00000200 /* jtag hreset */
620#define RSR_JHRS_SHIFT 9
621#define RSR_JSRS 0x00000100 /* jtag sreset status */
622#define RSR_JSRS_SHIFT 8
623#define RSR_CSHR 0x00000010 /* checkstop reset status */
624#define RSR_CSHR_SHIFT 4
625#define RSR_SWRS 0x00000008 /* software watchdog reset status */
626#define RSR_SWRS_SHIFT 3
627#define RSR_BMRS 0x00000004 /* bus monitop reset status */
628#define RSR_BMRS_SHIFT 2
629#define RSR_SRS 0x00000002 /* soft reset status */
630#define RSR_SRS_SHIFT 1
631#define RSR_HRS 0x00000001 /* hard reset status */
632#define RSR_HRS_SHIFT 0
633#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\
634 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
635 RSR_BMRS | RSR_SRS | RSR_HRS)
636/* RMR - Reset Mode Register
637 */
638#define RMR_CSRE 0x00000001 /* checkstop reset enable */
639#define RMR_CSRE_SHIFT 0
640#define RMR_RES ~(RMR_CSRE)
641
642/* RCR - Reset Control Register
643 */
644#define RCR_SWHR 0x00000002 /* software hard reset */
645#define RCR_SWSR 0x00000001 /* software soft reset */
646#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
647
648/* RCER - Reset Control Enable Register
649 */
650#define RCER_CRE 0x00000001 /* software hard reset */
651#define RCER_RES ~(RCER_CRE)
652
653/* SPMR - System PLL Mode Register
654 */
655#define SPMR_LBIUCM 0x80000000
656#define SPMR_DDRCM 0x40000000
657#define SPMR_SPMF 0x0F000000
658#define SPMR_CKID 0x00800000
659#define SPMR_CKID_SHIFT 23
660#define SPMR_COREPLL 0x007F0000
661#define SPMR_CEVCOD 0x000000C0
662#define SPMR_CEPDF 0x00000020
663#define SPMR_CEPMF 0x0000001F
664
665/* OCCR - Output Clock Control Register
666 */
667#define OCCR_PCICOE0 0x80000000
668#define OCCR_PCICOE1 0x40000000
669#define OCCR_PCICOE2 0x20000000
670#define OCCR_PCICOE3 0x10000000
671#define OCCR_PCICOE4 0x08000000
672#define OCCR_PCICOE5 0x04000000
673#define OCCR_PCICOE6 0x02000000
674#define OCCR_PCICOE7 0x01000000
675#define OCCR_PCICD0 0x00800000
676#define OCCR_PCICD1 0x00400000
677#define OCCR_PCICD2 0x00200000
678#define OCCR_PCICD3 0x00100000
679#define OCCR_PCICD4 0x00080000
680#define OCCR_PCICD5 0x00040000
681#define OCCR_PCICD6 0x00020000
682#define OCCR_PCICD7 0x00010000
683#define OCCR_PCI1CR 0x00000002
684#define OCCR_PCI2CR 0x00000001
685#define OCCR_PCICR OCCR_PCI1CR
686
687/* SCCR - System Clock Control Register
688 */
689#define SCCR_ENCCM 0x03000000
690#define SCCR_ENCCM_SHIFT 24
691#define SCCR_ENCCM_0 0x00000000
692#define SCCR_ENCCM_1 0x01000000
693#define SCCR_ENCCM_2 0x02000000
694#define SCCR_ENCCM_3 0x03000000
695
696#define SCCR_PCICM 0x00010000
697#define SCCR_PCICM_SHIFT 16
698
Dave Liu03051c32007-09-18 12:36:11 +0800699#if defined(CONFIG_MPC834X)
700/* SCCR bits - MPC834x specific */
Dave Liue0803132006-12-07 21:11:58 +0800701#define SCCR_TSEC1CM 0xc0000000
702#define SCCR_TSEC1CM_SHIFT 30
703#define SCCR_TSEC1CM_0 0x00000000
704#define SCCR_TSEC1CM_1 0x40000000
705#define SCCR_TSEC1CM_2 0x80000000
706#define SCCR_TSEC1CM_3 0xC0000000
707
708#define SCCR_TSEC2CM 0x30000000
709#define SCCR_TSEC2CM_SHIFT 28
710#define SCCR_TSEC2CM_0 0x00000000
711#define SCCR_TSEC2CM_1 0x10000000
712#define SCCR_TSEC2CM_2 0x20000000
713#define SCCR_TSEC2CM_3 0x30000000
Scott Woodd87c57b2007-04-16 14:31:55 -0500714
Dave Liu03051c32007-09-18 12:36:11 +0800715/* The MPH must have the same clock ratio as DR, unless its clock disabled */
716#define SCCR_USBMPHCM 0x00c00000
717#define SCCR_USBMPHCM_SHIFT 22
718#define SCCR_USBDRCM 0x00300000
719#define SCCR_USBDRCM_SHIFT 20
720#define SCCR_USBCM 0x00f00000
721#define SCCR_USBCM_SHIFT 20
722#define SCCR_USBCM_0 0x00000000
723#define SCCR_USBCM_1 0x00500000
724#define SCCR_USBCM_2 0x00A00000
725#define SCCR_USBCM_3 0x00F00000
726
Dave Liu555da612007-09-18 12:36:58 +0800727#elif defined(CONFIG_MPC8313)
Scott Woodd87c57b2007-04-16 14:31:55 -0500728/* TSEC1 bits are for TSEC2 as well */
729#define SCCR_TSEC1CM 0xc0000000
730#define SCCR_TSEC1CM_SHIFT 30
731#define SCCR_TSEC1CM_1 0x40000000
732#define SCCR_TSEC1CM_2 0x80000000
733#define SCCR_TSEC1CM_3 0xC0000000
734
735#define SCCR_TSEC1ON 0x20000000
Timur Tabidf33f6b2007-07-03 13:04:34 -0500736#define SCCR_TSEC1ON_SHIFT 29
Scott Woodd87c57b2007-04-16 14:31:55 -0500737#define SCCR_TSEC2ON 0x10000000
Timur Tabidf33f6b2007-07-03 13:04:34 -0500738#define SCCR_TSEC2ON_SHIFT 28
Scott Woodd87c57b2007-04-16 14:31:55 -0500739
Dave Liue0803132006-12-07 21:11:58 +0800740#define SCCR_USBDRCM 0x00300000
741#define SCCR_USBDRCM_SHIFT 20
Dave Liu03051c32007-09-18 12:36:11 +0800742#define SCCR_USBDRCM_0 0x00000000
743#define SCCR_USBDRCM_1 0x00100000
744#define SCCR_USBDRCM_2 0x00200000
745#define SCCR_USBDRCM_3 0x00300000
Dave Liue0803132006-12-07 21:11:58 +0800746
Dave Liu555da612007-09-18 12:36:58 +0800747#elif defined(CONFIG_MPC8315)
748/* SCCR bits - MPC8315 specific */
749#define SCCR_TSEC1CM 0xc0000000
750#define SCCR_TSEC1CM_SHIFT 30
751#define SCCR_TSEC1CM_0 0x00000000
752#define SCCR_TSEC1CM_1 0x40000000
753#define SCCR_TSEC1CM_2 0x80000000
754#define SCCR_TSEC1CM_3 0xC0000000
755
756#define SCCR_TSEC2CM 0x30000000
757#define SCCR_TSEC2CM_SHIFT 28
758#define SCCR_TSEC2CM_0 0x00000000
759#define SCCR_TSEC2CM_1 0x10000000
760#define SCCR_TSEC2CM_2 0x20000000
761#define SCCR_TSEC2CM_3 0x30000000
762
Dave Liu6f3931a2008-01-10 23:06:05 +0800763#define SCCR_USBDRCM 0x00c00000
764#define SCCR_USBDRCM_SHIFT 22
Dave Liu555da612007-09-18 12:36:58 +0800765#define SCCR_USBDRCM_0 0x00000000
Dave Liu6f3931a2008-01-10 23:06:05 +0800766#define SCCR_USBDRCM_1 0x00400000
767#define SCCR_USBDRCM_2 0x00800000
768#define SCCR_USBDRCM_3 0x00c00000
Dave Liu555da612007-09-18 12:36:58 +0800769
Dave Liu6f3931a2008-01-10 23:06:05 +0800770#define SCCR_PCIEXP1CM 0x00300000
771#define SCCR_PCIEXP2CM 0x000c0000
Dave Liu555da612007-09-18 12:36:58 +0800772
Dave Liu6f3931a2008-01-10 23:06:05 +0800773#define SCCR_SATA1CM 0x00003000
774#define SCCR_SATA1CM_SHIFT 12
775#define SCCR_SATACM 0x00003c00
776#define SCCR_SATACM_SHIFT 10
Dave Liu555da612007-09-18 12:36:58 +0800777#define SCCR_SATACM_0 0x00000000
Dave Liu6f3931a2008-01-10 23:06:05 +0800778#define SCCR_SATACM_1 0x00001400
779#define SCCR_SATACM_2 0x00002800
780#define SCCR_SATACM_3 0x00003c00
Dave Liu555da612007-09-18 12:36:58 +0800781
Dave Liu6f3931a2008-01-10 23:06:05 +0800782#define SCCR_TDMCM 0x00000030
783#define SCCR_TDMCM_SHIFT 4
Dave Liu555da612007-09-18 12:36:58 +0800784#define SCCR_TDMCM_0 0x00000000
Dave Liu6f3931a2008-01-10 23:06:05 +0800785#define SCCR_TDMCM_1 0x00000010
786#define SCCR_TDMCM_2 0x00000020
787#define SCCR_TDMCM_3 0x00000030
Dave Liu555da612007-09-18 12:36:58 +0800788
Dave Liu03051c32007-09-18 12:36:11 +0800789#elif defined(CONFIG_MPC837X)
790/* SCCR bits - MPC837x specific */
791#define SCCR_TSEC1CM 0xc0000000
792#define SCCR_TSEC1CM_SHIFT 30
793#define SCCR_TSEC1CM_0 0x00000000
794#define SCCR_TSEC1CM_1 0x40000000
795#define SCCR_TSEC1CM_2 0x80000000
796#define SCCR_TSEC1CM_3 0xC0000000
797
798#define SCCR_TSEC2CM 0x30000000
799#define SCCR_TSEC2CM_SHIFT 28
800#define SCCR_TSEC2CM_0 0x00000000
801#define SCCR_TSEC2CM_1 0x10000000
802#define SCCR_TSEC2CM_2 0x20000000
803#define SCCR_TSEC2CM_3 0x30000000
804
805#define SCCR_SDHCCM 0x0c000000
806#define SCCR_SDHCCM_SHIFT 26
807#define SCCR_SDHCCM_0 0x00000000
808#define SCCR_SDHCCM_1 0x04000000
809#define SCCR_SDHCCM_2 0x08000000
810#define SCCR_SDHCCM_3 0x0c000000
811
812#define SCCR_USBDRCM 0x00c00000
813#define SCCR_USBDRCM_SHIFT 22
814#define SCCR_USBDRCM_0 0x00000000
815#define SCCR_USBDRCM_1 0x00400000
816#define SCCR_USBDRCM_2 0x00800000
817#define SCCR_USBDRCM_3 0x00c00000
818
819#define SCCR_PCIEXP1CM 0x00300000
820#define SCCR_PCIEXP1CM_SHIFT 20
821#define SCCR_PCIEXP1CM_0 0x00000000
822#define SCCR_PCIEXP1CM_1 0x00100000
823#define SCCR_PCIEXP1CM_2 0x00200000
824#define SCCR_PCIEXP1CM_3 0x00300000
825
826#define SCCR_PCIEXP2CM 0x000c0000
827#define SCCR_PCIEXP2CM_SHIFT 18
828#define SCCR_PCIEXP2CM_0 0x00000000
829#define SCCR_PCIEXP2CM_1 0x00040000
830#define SCCR_PCIEXP2CM_2 0x00080000
831#define SCCR_PCIEXP2CM_3 0x000c0000
832
833/* All of the four SATA controllers must have the same clock ratio */
834#define SCCR_SATA1CM 0x000000c0
835#define SCCR_SATA1CM_SHIFT 6
836#define SCCR_SATACM 0x000000ff
837#define SCCR_SATACM_SHIFT 0
838#define SCCR_SATACM_0 0x00000000
839#define SCCR_SATACM_1 0x00000055
840#define SCCR_SATACM_2 0x000000aa
841#define SCCR_SATACM_3 0x000000ff
842#endif
Dave Liue0803132006-12-07 21:11:58 +0800843
Dave Liue0803132006-12-07 21:11:58 +0800844/* CSn_BDNS - Chip Select memory Bounds Register
845 */
846#define CSBNDS_SA 0x00FF0000
847#define CSBNDS_SA_SHIFT 8
848#define CSBNDS_EA 0x000000FF
849#define CSBNDS_EA_SHIFT 24
850
851/* CSn_CONFIG - Chip Select Configuration Register
852 */
853#define CSCONFIG_EN 0x80000000
854#define CSCONFIG_AP 0x00800000
855#define CSCONFIG_ROW_BIT 0x00000700
856#define CSCONFIG_ROW_BIT_12 0x00000000
857#define CSCONFIG_ROW_BIT_13 0x00000100
858#define CSCONFIG_ROW_BIT_14 0x00000200
859#define CSCONFIG_COL_BIT 0x00000007
860#define CSCONFIG_COL_BIT_8 0x00000000
861#define CSCONFIG_COL_BIT_9 0x00000001
862#define CSCONFIG_COL_BIT_10 0x00000002
863#define CSCONFIG_COL_BIT_11 0x00000003
864
Scott Woodd87c57b2007-04-16 14:31:55 -0500865/* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
866 */
867#define TIMING_CFG0_RWT 0xC0000000
868#define TIMING_CFG0_RWT_SHIFT 30
869#define TIMING_CFG0_WRT 0x30000000
870#define TIMING_CFG0_WRT_SHIFT 28
871#define TIMING_CFG0_RRT 0x0C000000
872#define TIMING_CFG0_RRT_SHIFT 26
873#define TIMING_CFG0_WWT 0x03000000
874#define TIMING_CFG0_WWT_SHIFT 24
875#define TIMING_CFG0_ACT_PD_EXIT 0x00700000
876#define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20
877#define TIMING_CFG0_PRE_PD_EXIT 0x00070000
878#define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16
879#define TIMING_CFG0_ODT_PD_EXIT 0x00000F00
880#define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8
881#define TIMING_CFG0_MRS_CYC 0x00000F00
882#define TIMING_CFG0_MRS_CYC_SHIFT 0
883
Dave Liue0803132006-12-07 21:11:58 +0800884/* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
885 */
886#define TIMING_CFG1_PRETOACT 0x70000000
887#define TIMING_CFG1_PRETOACT_SHIFT 28
888#define TIMING_CFG1_ACTTOPRE 0x0F000000
889#define TIMING_CFG1_ACTTOPRE_SHIFT 24
890#define TIMING_CFG1_ACTTORW 0x00700000
891#define TIMING_CFG1_ACTTORW_SHIFT 20
892#define TIMING_CFG1_CASLAT 0x00070000
893#define TIMING_CFG1_CASLAT_SHIFT 16
894#define TIMING_CFG1_REFREC 0x0000F000
895#define TIMING_CFG1_REFREC_SHIFT 12
896#define TIMING_CFG1_WRREC 0x00000700
897#define TIMING_CFG1_WRREC_SHIFT 8
898#define TIMING_CFG1_ACTTOACT 0x00000070
899#define TIMING_CFG1_ACTTOACT_SHIFT 4
900#define TIMING_CFG1_WRTORD 0x00000007
901#define TIMING_CFG1_WRTORD_SHIFT 0
902#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
903#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
904
905/* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
906 */
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800907#define TIMING_CFG2_CPO 0x0F800000
908#define TIMING_CFG2_CPO_SHIFT 23
Dave Liue0803132006-12-07 21:11:58 +0800909#define TIMING_CFG2_ACSM 0x00080000
910#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
911#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
912#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
913
Scott Woodd87c57b2007-04-16 14:31:55 -0500914#define TIMING_CFG2_ADD_LAT 0x70000000
915#define TIMING_CFG2_ADD_LAT_SHIFT 28
916#define TIMING_CFG2_WR_LAT_DELAY 0x00380000
917#define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19
918#define TIMING_CFG2_RD_TO_PRE 0x0000E000
919#define TIMING_CFG2_RD_TO_PRE_SHIFT 13
920#define TIMING_CFG2_CKE_PLS 0x000001C0
921#define TIMING_CFG2_CKE_PLS_SHIFT 6
922#define TIMING_CFG2_FOUR_ACT 0x0000003F
923#define TIMING_CFG2_FOUR_ACT_SHIFT 0
924
Dave Liue0803132006-12-07 21:11:58 +0800925/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
926 */
927#define SDRAM_CFG_MEM_EN 0x80000000
928#define SDRAM_CFG_SREN 0x40000000
929#define SDRAM_CFG_ECC_EN 0x20000000
930#define SDRAM_CFG_RD_EN 0x10000000
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500931#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
932#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
933#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
Dave Liue0803132006-12-07 21:11:58 +0800934#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
935#define SDRAM_CFG_DYN_PWR 0x00200000
936#define SDRAM_CFG_32_BE 0x00080000
937#define SDRAM_CFG_8_BE 0x00040000
938#define SDRAM_CFG_NCAP 0x00020000
939#define SDRAM_CFG_2T_EN 0x00008000
Scott Woodd87c57b2007-04-16 14:31:55 -0500940#define SDRAM_CFG_BI 0x00000001
Dave Liue0803132006-12-07 21:11:58 +0800941
942/* DDR_SDRAM_MODE - DDR SDRAM Mode Register
943 */
944#define SDRAM_MODE_ESD 0xFFFF0000
945#define SDRAM_MODE_ESD_SHIFT 16
946#define SDRAM_MODE_SD 0x0000FFFF
947#define SDRAM_MODE_SD_SHIFT 0
948#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
949#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
950#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
951#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
952#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
953#define DDR_MODE_WEAK 0x0002 /* weak drivers */
954#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
955#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
956#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
957#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
958#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
959#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
960#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
961#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
962#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
963#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
964#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */
965#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
966#define DDR_MODE_MODEREG 0x0000 /* select mode register */
967
968/* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
969 */
970#define SDRAM_INTERVAL_REFINT 0x3FFF0000
971#define SDRAM_INTERVAL_REFINT_SHIFT 16
972#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
973#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
974
975/* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
976 */
977#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
978#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
979#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
980#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
981#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
982
983/* ECC_ERR_INJECT - Memory data path error injection mask ECC
984 */
985#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */
986#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */
987#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */
988#define ECC_ERR_INJECT_EEIM_SHIFT 0
989
990/* CAPTURE_ECC - Memory data path read capture ECC
991 */
992#define CAPTURE_ECC_ECE (0xff000000>>24)
993#define CAPTURE_ECC_ECE_SHIFT 0
994
995/* ERR_DETECT - Memory error detect
996 */
997#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */
998#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */
999#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */
1000#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */
1001
1002/* ERR_DISABLE - Memory error disable
1003 */
1004#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */
1005#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */
1006#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */
1007#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\
1008 ECC_ERROR_DISABLE_MBED)
1009/* ERR_INT_EN - Memory error interrupt enable
1010 */
1011#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */
1012#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */
1013#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */
1014#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\
1015 ECC_ERR_INT_EN_MSEE)
1016/* CAPTURE_ATTRIBUTES - Memory error attributes capture
1017 */
1018#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */
1019#define ECC_CAPT_ATTR_BNUM_SHIFT 28
1020#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */
1021#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
1022#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
1023#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
1024#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
1025#define ECC_CAPT_ATTR_TSIZ_SHIFT 24
1026#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */
1027#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
1028#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
1029#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
1030#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
1031#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
1032#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
1033#define ECC_CAPT_ATTR_TSRC_I2C 0x9
1034#define ECC_CAPT_ATTR_TSRC_JTAG 0xA
1035#define ECC_CAPT_ATTR_TSRC_PCI1 0xD
1036#define ECC_CAPT_ATTR_TSRC_PCI2 0xE
1037#define ECC_CAPT_ATTR_TSRC_DMA 0xF
1038#define ECC_CAPT_ATTR_TSRC_SHIFT 16
1039#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */
1040#define ECC_CAPT_ATTR_TTYP_WRITE 0x1
1041#define ECC_CAPT_ATTR_TTYP_READ 0x2
1042#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
1043#define ECC_CAPT_ATTR_TTYP_SHIFT 12
1044#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */
1045
1046/* ERR_SBE - Single bit ECC memory error management
1047 */
1048#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */
1049#define ECC_ERROR_MAN_SBET_SHIFT 16
1050#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */
1051#define ECC_ERROR_MAN_SBEC_SHIFT 0
1052
1053/* BR - Base Registers
1054 */
1055#define BR0 0x5000 /* Register offset to immr */
1056#define BR1 0x5008
1057#define BR2 0x5010
1058#define BR3 0x5018
1059#define BR4 0x5020
1060#define BR5 0x5028
1061#define BR6 0x5030
1062#define BR7 0x5038
1063
1064#define BR_BA 0xFFFF8000
1065#define BR_BA_SHIFT 15
1066#define BR_PS 0x00001800
1067#define BR_PS_SHIFT 11
1068#define BR_PS_8 0x00000800 /* Port Size 8 bit */
1069#define BR_PS_16 0x00001000 /* Port Size 16 bit */
1070#define BR_PS_32 0x00001800 /* Port Size 32 bit */
1071#define BR_DECC 0x00000600
1072#define BR_DECC_SHIFT 9
Scott Woodd87c57b2007-04-16 14:31:55 -05001073#define BR_DECC_OFF 0x00000000
1074#define BR_DECC_CHK 0x00000200
1075#define BR_DECC_CHK_GEN 0x00000400
Dave Liue0803132006-12-07 21:11:58 +08001076#define BR_WP 0x00000100
1077#define BR_WP_SHIFT 8
1078#define BR_MSEL 0x000000E0
1079#define BR_MSEL_SHIFT 5
1080#define BR_MS_GPCM 0x00000000 /* GPCM */
Scott Woodd87c57b2007-04-16 14:31:55 -05001081#define BR_MS_FCM 0x00000020 /* FCM */
Dave Liue0803132006-12-07 21:11:58 +08001082#define BR_MS_SDRAM 0x00000060 /* SDRAM */
1083#define BR_MS_UPMA 0x00000080 /* UPMA */
1084#define BR_MS_UPMB 0x000000A0 /* UPMB */
1085#define BR_MS_UPMC 0x000000C0 /* UPMC */
Dave Liu03051c32007-09-18 12:36:11 +08001086#if !defined(CONFIG_MPC834X)
Dave Liue0803132006-12-07 21:11:58 +08001087#define BR_ATOM 0x0000000C
1088#define BR_ATOM_SHIFT 2
1089#endif
1090#define BR_V 0x00000001
1091#define BR_V_SHIFT 0
1092
Kumar Gala3e78a312007-01-30 14:08:30 -06001093#if defined(CONFIG_MPC834X)
Dave Liue0803132006-12-07 21:11:58 +08001094#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
Dave Liu03051c32007-09-18 12:36:11 +08001095#else
Dave Liue0803132006-12-07 21:11:58 +08001096#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
1097#endif
1098
1099/* OR - Option Registers
1100 */
1101#define OR0 0x5004 /* Register offset to immr */
1102#define OR1 0x500C
1103#define OR2 0x5014
1104#define OR3 0x501C
1105#define OR4 0x5024
1106#define OR5 0x502C
1107#define OR6 0x5034
1108#define OR7 0x503C
1109
1110#define OR_GPCM_AM 0xFFFF8000
Marian Balakowicze6f2e902005-10-11 19:09:42 +02001111#define OR_GPCM_AM_SHIFT 15
Dave Liue0803132006-12-07 21:11:58 +08001112#define OR_GPCM_BCTLD 0x00001000
Marian Balakowicze6f2e902005-10-11 19:09:42 +02001113#define OR_GPCM_BCTLD_SHIFT 12
Dave Liue0803132006-12-07 21:11:58 +08001114#define OR_GPCM_CSNT 0x00000800
Marian Balakowicze6f2e902005-10-11 19:09:42 +02001115#define OR_GPCM_CSNT_SHIFT 11
Dave Liue0803132006-12-07 21:11:58 +08001116#define OR_GPCM_ACS 0x00000600
1117#define OR_GPCM_ACS_SHIFT 9
1118#define OR_GPCM_ACS_0b10 0x00000400
1119#define OR_GPCM_ACS_0b11 0x00000600
1120#define OR_GPCM_XACS 0x00000100
1121#define OR_GPCM_XACS_SHIFT 8
1122#define OR_GPCM_SCY 0x000000F0
1123#define OR_GPCM_SCY_SHIFT 4
1124#define OR_GPCM_SCY_1 0x00000010
1125#define OR_GPCM_SCY_2 0x00000020
1126#define OR_GPCM_SCY_3 0x00000030
1127#define OR_GPCM_SCY_4 0x00000040
1128#define OR_GPCM_SCY_5 0x00000050
1129#define OR_GPCM_SCY_6 0x00000060
1130#define OR_GPCM_SCY_7 0x00000070
1131#define OR_GPCM_SCY_8 0x00000080
1132#define OR_GPCM_SCY_9 0x00000090
1133#define OR_GPCM_SCY_10 0x000000a0
1134#define OR_GPCM_SCY_11 0x000000b0
1135#define OR_GPCM_SCY_12 0x000000c0
1136#define OR_GPCM_SCY_13 0x000000d0
1137#define OR_GPCM_SCY_14 0x000000e0
1138#define OR_GPCM_SCY_15 0x000000f0
1139#define OR_GPCM_SETA 0x00000008
1140#define OR_GPCM_SETA_SHIFT 3
1141#define OR_GPCM_TRLX 0x00000004
1142#define OR_GPCM_TRLX_SHIFT 2
1143#define OR_GPCM_EHTR 0x00000002
1144#define OR_GPCM_EHTR_SHIFT 1
1145#define OR_GPCM_EAD 0x00000001
1146#define OR_GPCM_EAD_SHIFT 0
Eran Libertyf046ccd2005-07-28 10:08:46 -05001147
Scott Woodd87c57b2007-04-16 14:31:55 -05001148#define OR_FCM_AM 0xFFFF8000
1149#define OR_FCM_AM_SHIFT 15
1150#define OR_FCM_BCTLD 0x00001000
1151#define OR_FCM_BCTLD_SHIFT 12
1152#define OR_FCM_PGS 0x00000400
1153#define OR_FCM_PGS_SHIFT 10
1154#define OR_FCM_CSCT 0x00000200
1155#define OR_FCM_CSCT_SHIFT 9
1156#define OR_FCM_CST 0x00000100
1157#define OR_FCM_CST_SHIFT 8
1158#define OR_FCM_CHT 0x00000080
1159#define OR_FCM_CHT_SHIFT 7
1160#define OR_FCM_SCY 0x00000070
1161#define OR_FCM_SCY_SHIFT 4
1162#define OR_FCM_SCY_1 0x00000010
1163#define OR_FCM_SCY_2 0x00000020
1164#define OR_FCM_SCY_3 0x00000030
1165#define OR_FCM_SCY_4 0x00000040
1166#define OR_FCM_SCY_5 0x00000050
1167#define OR_FCM_SCY_6 0x00000060
1168#define OR_FCM_SCY_7 0x00000070
1169#define OR_FCM_RST 0x00000008
1170#define OR_FCM_RST_SHIFT 3
1171#define OR_FCM_TRLX 0x00000004
1172#define OR_FCM_TRLX_SHIFT 2
1173#define OR_FCM_EHTR 0x00000002
1174#define OR_FCM_EHTR_SHIFT 1
1175
Dave Liue0803132006-12-07 21:11:58 +08001176#define OR_UPM_AM 0xFFFF8000
1177#define OR_UPM_AM_SHIFT 15
1178#define OR_UPM_XAM 0x00006000
1179#define OR_UPM_XAM_SHIFT 13
1180#define OR_UPM_BCTLD 0x00001000
1181#define OR_UPM_BCTLD_SHIFT 12
1182#define OR_UPM_BI 0x00000100
1183#define OR_UPM_BI_SHIFT 8
1184#define OR_UPM_TRLX 0x00000004
1185#define OR_UPM_TRLX_SHIFT 2
1186#define OR_UPM_EHTR 0x00000002
1187#define OR_UPM_EHTR_SHIFT 1
1188#define OR_UPM_EAD 0x00000001
1189#define OR_UPM_EAD_SHIFT 0
Eran Libertyf046ccd2005-07-28 10:08:46 -05001190
Dave Liue0803132006-12-07 21:11:58 +08001191#define OR_SDRAM_AM 0xFFFF8000
1192#define OR_SDRAM_AM_SHIFT 15
1193#define OR_SDRAM_XAM 0x00006000
1194#define OR_SDRAM_XAM_SHIFT 13
1195#define OR_SDRAM_COLS 0x00001C00
1196#define OR_SDRAM_COLS_SHIFT 10
1197#define OR_SDRAM_ROWS 0x000001C0
1198#define OR_SDRAM_ROWS_SHIFT 6
1199#define OR_SDRAM_PMSEL 0x00000020
1200#define OR_SDRAM_PMSEL_SHIFT 5
1201#define OR_SDRAM_EAD 0x00000001
1202#define OR_SDRAM_EAD_SHIFT 0
Eran Libertyf046ccd2005-07-28 10:08:46 -05001203
Timur Tabi7a78f142007-01-31 15:54:29 -06001204#define OR_AM_32KB 0xFFFF8000
1205#define OR_AM_64KB 0xFFFF0000
1206#define OR_AM_128KB 0xFFFE0000
1207#define OR_AM_256KB 0xFFFC0000
1208#define OR_AM_512KB 0xFFF80000
1209#define OR_AM_1MB 0xFFF00000
1210#define OR_AM_2MB 0xFFE00000
1211#define OR_AM_4MB 0xFFC00000
1212#define OR_AM_8MB 0xFF800000
1213#define OR_AM_16MB 0xFF000000
1214#define OR_AM_32MB 0xFE000000
1215#define OR_AM_64MB 0xFC000000
1216#define OR_AM_128MB 0xF8000000
1217#define OR_AM_256MB 0xF0000000
1218#define OR_AM_512MB 0xE0000000
1219#define OR_AM_1GB 0xC0000000
1220#define OR_AM_2GB 0x80000000
1221#define OR_AM_4GB 0x00000000
1222
1223#define LBLAWAR_EN 0x80000000
1224#define LBLAWAR_4KB 0x0000000B
1225#define LBLAWAR_8KB 0x0000000C
1226#define LBLAWAR_16KB 0x0000000D
1227#define LBLAWAR_32KB 0x0000000E
1228#define LBLAWAR_64KB 0x0000000F
1229#define LBLAWAR_128KB 0x00000010
1230#define LBLAWAR_256KB 0x00000011
1231#define LBLAWAR_512KB 0x00000012
1232#define LBLAWAR_1MB 0x00000013
1233#define LBLAWAR_2MB 0x00000014
1234#define LBLAWAR_4MB 0x00000015
1235#define LBLAWAR_8MB 0x00000016
1236#define LBLAWAR_16MB 0x00000017
1237#define LBLAWAR_32MB 0x00000018
1238#define LBLAWAR_64MB 0x00000019
1239#define LBLAWAR_128MB 0x0000001A
1240#define LBLAWAR_256MB 0x0000001B
1241#define LBLAWAR_512MB 0x0000001C
1242#define LBLAWAR_1GB 0x0000001D
1243#define LBLAWAR_2GB 0x0000001E
1244
Dave Liue0803132006-12-07 21:11:58 +08001245/* LBCR - Local Bus Configuration Register
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001246 */
Dave Liue0803132006-12-07 21:11:58 +08001247#define LBCR_LDIS 0x80000000
1248#define LBCR_LDIS_SHIFT 31
1249#define LBCR_BCTLC 0x00C00000
1250#define LBCR_BCTLC_SHIFT 22
1251#define LBCR_LPBSE 0x00020000
1252#define LBCR_LPBSE_SHIFT 17
1253#define LBCR_EPAR 0x00010000
1254#define LBCR_EPAR_SHIFT 16
1255#define LBCR_BMT 0x0000FF00
1256#define LBCR_BMT_SHIFT 8
Eran Libertyf046ccd2005-07-28 10:08:46 -05001257
Dave Liue0803132006-12-07 21:11:58 +08001258/* LCRR - Clock Ratio Register
Eran Libertyf046ccd2005-07-28 10:08:46 -05001259 */
Dave Liue0803132006-12-07 21:11:58 +08001260#define LCRR_DBYP 0x80000000
1261#define LCRR_DBYP_SHIFT 31
1262#define LCRR_BUFCMDC 0x30000000
1263#define LCRR_BUFCMDC_SHIFT 28
1264#define LCRR_BUFCMDC_1 0x10000000
1265#define LCRR_BUFCMDC_2 0x20000000
1266#define LCRR_BUFCMDC_3 0x30000000
1267#define LCRR_BUFCMDC_4 0x00000000
1268#define LCRR_ECL 0x03000000
1269#define LCRR_ECL_SHIFT 24
1270#define LCRR_ECL_4 0x00000000
1271#define LCRR_ECL_5 0x01000000
1272#define LCRR_ECL_6 0x02000000
1273#define LCRR_ECL_7 0x03000000
1274#define LCRR_EADC 0x00030000
1275#define LCRR_EADC_SHIFT 16
1276#define LCRR_EADC_1 0x00010000
1277#define LCRR_EADC_2 0x00020000
1278#define LCRR_EADC_3 0x00030000
1279#define LCRR_EADC_4 0x00000000
1280#define LCRR_CLKDIV 0x0000000F
1281#define LCRR_CLKDIV_SHIFT 0
1282#define LCRR_CLKDIV_2 0x00000002
1283#define LCRR_CLKDIV_4 0x00000004
1284#define LCRR_CLKDIV_8 0x00000008
Eran Libertyf046ccd2005-07-28 10:08:46 -05001285
Dave Liue0803132006-12-07 21:11:58 +08001286/* DMAMR - DMA Mode Register
Eran Libertyf046ccd2005-07-28 10:08:46 -05001287 */
Dave Liue0803132006-12-07 21:11:58 +08001288#define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */
1289#define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */
1290#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */
1291#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */
1292#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */
1293#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */
1294#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */
1295#define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */
Eran Libertyf046ccd2005-07-28 10:08:46 -05001296
Dave Liue0803132006-12-07 21:11:58 +08001297/* DMASR - DMA Status Register
Dave Liuf6eda7f2006-10-25 14:41:21 -05001298 */
Dave Liue0803132006-12-07 21:11:58 +08001299#define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */
1300#define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */
Dave Liuf6eda7f2006-10-25 14:41:21 -05001301
Dave Liue0803132006-12-07 21:11:58 +08001302/* CONFIG_ADDRESS - PCI Config Address Register
1303 */
1304#define PCI_CONFIG_ADDRESS_EN 0x80000000
1305#define PCI_CONFIG_ADDRESS_BN_SHIFT 16
1306#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
1307#define PCI_CONFIG_ADDRESS_DN_SHIFT 11
1308#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
1309#define PCI_CONFIG_ADDRESS_FN_SHIFT 8
1310#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
1311#define PCI_CONFIG_ADDRESS_RN_SHIFT 0
1312#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
Dave Liu5f820432006-11-03 19:33:44 -06001313
Dave Liue0803132006-12-07 21:11:58 +08001314/* POTAR - PCI Outbound Translation Address Register
1315 */
1316#define POTAR_TA_MASK 0x000fffff
1317
1318/* POBAR - PCI Outbound Base Address Register
1319 */
1320#define POBAR_BA_MASK 0x000fffff
1321
1322/* POCMR - PCI Outbound Comparision Mask Register
1323 */
1324#define POCMR_EN 0x80000000
1325#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */
1326#define POCMR_SE 0x20000000 /* streaming enable */
1327#define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */
1328#define POCMR_CM_MASK 0x000fffff
1329#define POCMR_CM_4G 0x00000000
1330#define POCMR_CM_2G 0x00080000
1331#define POCMR_CM_1G 0x000C0000
1332#define POCMR_CM_512M 0x000E0000
1333#define POCMR_CM_256M 0x000F0000
1334#define POCMR_CM_128M 0x000F8000
1335#define POCMR_CM_64M 0x000FC000
1336#define POCMR_CM_32M 0x000FE000
1337#define POCMR_CM_16M 0x000FF000
1338#define POCMR_CM_8M 0x000FF800
1339#define POCMR_CM_4M 0x000FFC00
1340#define POCMR_CM_2M 0x000FFE00
1341#define POCMR_CM_1M 0x000FFF00
1342#define POCMR_CM_512K 0x000FFF80
1343#define POCMR_CM_256K 0x000FFFC0
1344#define POCMR_CM_128K 0x000FFFE0
1345#define POCMR_CM_64K 0x000FFFF0
1346#define POCMR_CM_32K 0x000FFFF8
1347#define POCMR_CM_16K 0x000FFFFC
1348#define POCMR_CM_8K 0x000FFFFE
1349#define POCMR_CM_4K 0x000FFFFF
1350
1351/* PITAR - PCI Inbound Translation Address Register
1352 */
1353#define PITAR_TA_MASK 0x000fffff
1354
1355/* PIBAR - PCI Inbound Base/Extended Address Register
1356 */
1357#define PIBAR_MASK 0xffffffff
1358#define PIEBAR_EBA_MASK 0x000fffff
1359
1360/* PIWAR - PCI Inbound Windows Attributes Register
1361 */
1362#define PIWAR_EN 0x80000000
1363#define PIWAR_PF 0x20000000
1364#define PIWAR_RTT_MASK 0x000f0000
1365#define PIWAR_RTT_NO_SNOOP 0x00040000
1366#define PIWAR_RTT_SNOOP 0x00050000
1367#define PIWAR_WTT_MASK 0x0000f000
1368#define PIWAR_WTT_NO_SNOOP 0x00004000
1369#define PIWAR_WTT_SNOOP 0x00005000
1370#define PIWAR_IWS_MASK 0x0000003F
1371#define PIWAR_IWS_4K 0x0000000B
1372#define PIWAR_IWS_8K 0x0000000C
1373#define PIWAR_IWS_16K 0x0000000D
1374#define PIWAR_IWS_32K 0x0000000E
1375#define PIWAR_IWS_64K 0x0000000F
1376#define PIWAR_IWS_128K 0x00000010
1377#define PIWAR_IWS_256K 0x00000011
1378#define PIWAR_IWS_512K 0x00000012
1379#define PIWAR_IWS_1M 0x00000013
1380#define PIWAR_IWS_2M 0x00000014
1381#define PIWAR_IWS_4M 0x00000015
1382#define PIWAR_IWS_8M 0x00000016
1383#define PIWAR_IWS_16M 0x00000017
1384#define PIWAR_IWS_32M 0x00000018
1385#define PIWAR_IWS_64M 0x00000019
1386#define PIWAR_IWS_128M 0x0000001A
1387#define PIWAR_IWS_256M 0x0000001B
1388#define PIWAR_IWS_512M 0x0000001C
1389#define PIWAR_IWS_1G 0x0000001D
1390#define PIWAR_IWS_2G 0x0000001E
Dave Liuf6eda7f2006-10-25 14:41:21 -05001391
Scott Woodd87c57b2007-04-16 14:31:55 -05001392/* PMCCR1 - PCI Configuration Register 1
1393 */
1394#define PMCCR1_POWER_OFF 0x00000020
1395
1396/* FMR - Flash Mode Register
1397 */
1398#define FMR_CWTO 0x0000F000
1399#define FMR_CWTO_SHIFT 12
1400#define FMR_BOOT 0x00000800
1401#define FMR_ECCM 0x00000100
1402#define FMR_AL 0x00000030
1403#define FMR_AL_SHIFT 4
1404#define FMR_OP 0x00000003
1405#define FMR_OP_SHIFT 0
1406
1407/* FIR - Flash Instruction Register
1408 */
1409#define FIR_OP0 0xF0000000
1410#define FIR_OP0_SHIFT 28
1411#define FIR_OP1 0x0F000000
1412#define FIR_OP1_SHIFT 24
1413#define FIR_OP2 0x00F00000
1414#define FIR_OP2_SHIFT 20
1415#define FIR_OP3 0x000F0000
1416#define FIR_OP3_SHIFT 16
1417#define FIR_OP4 0x0000F000
1418#define FIR_OP4_SHIFT 12
1419#define FIR_OP5 0x00000F00
1420#define FIR_OP5_SHIFT 8
1421#define FIR_OP6 0x000000F0
1422#define FIR_OP6_SHIFT 4
1423#define FIR_OP7 0x0000000F
1424#define FIR_OP7_SHIFT 0
1425#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
1426#define FIR_OP_CA 0x1 /* Issue current column address */
1427#define FIR_OP_PA 0x2 /* Issue current block+page address */
1428#define FIR_OP_UA 0x3 /* Issue user defined address */
1429#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
1430#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
1431#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
1432#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
1433#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
1434#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
1435#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
1436#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
1437#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
1438#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
1439#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
1440#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */
1441
1442/* FCR - Flash Command Register
1443 */
1444#define FCR_CMD0 0xFF000000
1445#define FCR_CMD0_SHIFT 24
1446#define FCR_CMD1 0x00FF0000
1447#define FCR_CMD1_SHIFT 16
1448#define FCR_CMD2 0x0000FF00
Wolfgang Denk1636d1c2007-06-22 23:59:00 +02001449#define FCR_CMD2_SHIFT 8
Scott Woodd87c57b2007-04-16 14:31:55 -05001450#define FCR_CMD3 0x000000FF
1451#define FCR_CMD3_SHIFT 0
1452
1453/* FBAR - Flash Block Address Register
1454 */
1455#define FBAR_BLK 0x00FFFFFF
1456
1457/* FPAR - Flash Page Address Register
1458 */
1459#define FPAR_SP_PI 0x00007C00
1460#define FPAR_SP_PI_SHIFT 10
1461#define FPAR_SP_MS 0x00000200
1462#define FPAR_SP_CI 0x000001FF
1463#define FPAR_SP_CI_SHIFT 0
1464#define FPAR_LP_PI 0x0003F000
1465#define FPAR_LP_PI_SHIFT 12
1466#define FPAR_LP_MS 0x00000800
1467#define FPAR_LP_CI 0x000007FF
1468#define FPAR_LP_CI_SHIFT 0
1469
1470/* LTESR - Transfer Error Status Register
1471 */
1472#define LTESR_BM 0x80000000
Wolfgang Denk1636d1c2007-06-22 23:59:00 +02001473#define LTESR_FCT 0x40000000
1474#define LTESR_PAR 0x20000000
Scott Woodd87c57b2007-04-16 14:31:55 -05001475#define LTESR_WP 0x04000000
1476#define LTESR_ATMW 0x00800000
1477#define LTESR_ATMR 0x00400000
1478#define LTESR_CS 0x00080000
1479#define LTESR_CC 0x00000001
1480
Dave Liu03051c32007-09-18 12:36:11 +08001481/* DDRCDR - DDR Control Driver Register
Scott Woodd87c57b2007-04-16 14:31:55 -05001482 */
1483#define DDRCDR_EN 0x40000000
1484#define DDRCDR_PZ 0x3C000000
1485#define DDRCDR_PZ_MAXZ 0x00000000
1486#define DDRCDR_PZ_HIZ 0x20000000
1487#define DDRCDR_PZ_NOMZ 0x30000000
1488#define DDRCDR_PZ_LOZ 0x38000000
1489#define DDRCDR_PZ_MINZ 0x3C000000
1490#define DDRCDR_NZ 0x3C000000
1491#define DDRCDR_NZ_MAXZ 0x00000000
1492#define DDRCDR_NZ_HIZ 0x02000000
1493#define DDRCDR_NZ_NOMZ 0x03000000
1494#define DDRCDR_NZ_LOZ 0x03800000
1495#define DDRCDR_NZ_MINZ 0x03C00000
1496#define DDRCDR_ODT 0x00080000
1497#define DDRCDR_DDR_CFG 0x00040000
1498#define DDRCDR_M_ODR 0x00000002
1499#define DDRCDR_Q_DRN 0x00000001
1500
Scott Wood49ea3b62007-04-16 14:34:21 -05001501#ifndef __ASSEMBLY__
1502struct pci_region;
1503void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);
1504#endif
1505
Eran Libertyf046ccd2005-07-28 10:08:46 -05001506#endif /* __MPC83XX_H__ */