blob: 0d9a412fd5e04c5efbfc602ef30f413f1fa3c264 [file] [log] [blame]
Michal Simek0435a822019-02-19 11:32:24 +01001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018 Xilinx, Inc.
4 */
5
6#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
7#define _DT_BINDINGS_ZYNQMP_POWER_H
8
9#define PD_USB_0 22
10#define PD_USB_1 23
11#define PD_TTC_0 24
12#define PD_TTC_1 25
13#define PD_TTC_2 26
14#define PD_TTC_3 27
15#define PD_SATA 28
16#define PD_ETH_0 29
17#define PD_ETH_1 30
18#define PD_ETH_2 31
19#define PD_ETH_3 32
20#define PD_UART_0 33
21#define PD_UART_1 34
22#define PD_SPI_0 35
23#define PD_SPI_1 36
24#define PD_I2C_0 37
25#define PD_I2C_1 38
26#define PD_SD_0 39
27#define PD_SD_1 40
28#define PD_DP 41
29#define PD_GDMA 42
30#define PD_ADMA 43
31#define PD_NAND 44
32#define PD_QSPI 45
33#define PD_GPIO 46
34#define PD_CAN_0 47
35#define PD_CAN_1 48
36#define PD_GPU 58
37#define PD_PCIE 59
38
39#endif