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Masahiro Yamadad7505752017-08-29 01:06:15 +09001/*
2 * Copyright (C) 2016-2017 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include "clk-uniphier.h"
9
Masahiro Yamada7d9927c2017-10-14 02:21:19 +090010/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */
11#define UNIPHIER_LD4_SYS_CLK_NAND(_id) \
12 UNIPHIER_CLK_RATE(128, 200000000), \
13 UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2)
14
15#define UNIPHIER_LD11_SYS_CLK_NAND(_id) \
16 UNIPHIER_CLK_RATE(128, 200000000), \
17 UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0)
18
Masahiro Yamadad6c7ee72017-10-13 19:21:59 +090019const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
20#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8) ||\
21 defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\
22 defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
Masahiro Yamada7d9927c2017-10-14 02:21:19 +090023 UNIPHIER_LD4_SYS_CLK_NAND(2),
Kunihiko Hayashi461766c2018-04-18 10:05:33 +090024 UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */
25 UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */
Masahiro Yamadad6c7ee72017-10-13 19:21:59 +090026 UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */
Kunihiko Hayashi461766c2018-04-18 10:05:33 +090027 UNIPHIER_CLK_GATE_SIMPLE(10, 0x2260, 0), /* ether-phy (Pro4) */
Masahiro Yamadad6c7ee72017-10-13 19:21:59 +090028 UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6), /* gio (Pro4, Pro5) */
29 UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */
30 UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */
31 UNIPHIER_CLK_GATE_SIMPLE(16, 0x2104, 19), /* usb30-phy (PXs2) */
32 UNIPHIER_CLK_GATE_SIMPLE(20, 0x2104, 20), /* usb31-phy (PXs2) */
33 { /* sentinel */ }
34#endif
Masahiro Yamadad7505752017-08-29 01:06:15 +090035};
36
Masahiro Yamadad6c7ee72017-10-13 19:21:59 +090037const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
38#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
Masahiro Yamada7d9927c2017-10-14 02:21:19 +090039 UNIPHIER_LD11_SYS_CLK_NAND(2),
Kunihiko Hayashi461766c2018-04-18 10:05:33 +090040 UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */
Masahiro Yamadad6c7ee72017-10-13 19:21:59 +090041 UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */
42 UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */
43 UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */
44 UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 13), /* usb30-phy1 (LD20) */
45 { /* sentinel */ }
46#endif
Masahiro Yamadad7505752017-08-29 01:06:15 +090047};
Masahiro Yamadaab054062017-10-13 19:22:00 +090048
49const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
50#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
Masahiro Yamada7d9927c2017-10-14 02:21:19 +090051 UNIPHIER_LD11_SYS_CLK_NAND(2),
Kunihiko Hayashi461766c2018-04-18 10:05:33 +090052 UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */
53 UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */
Masahiro Yamadaab054062017-10-13 19:22:00 +090054 UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */
55 UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5), /* usb31-0 (gio1) */
56 UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6), /* usb31-1 (gio1-1) */
57 UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 16), /* usb30-phy0 */
58 UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 18), /* usb30-phy1 */
59 UNIPHIER_CLK_GATE_SIMPLE(18, 0x210c, 20), /* usb30-phy2 */
60 UNIPHIER_CLK_GATE_SIMPLE(20, 0x210c, 17), /* usb31-phy0 */
61 UNIPHIER_CLK_GATE_SIMPLE(21, 0x210c, 19), /* usb31-phy1 */
62 { /* sentinel */ }
63#endif
64};