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Vladimir Barinov60c04672015-02-14 01:06:13 +03001/*
2 * include/configs/porter.h
3 * This file is Porter board configuration.
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 * Copyright (C) 2015 Cogent Embedded, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0
9 */
10
11#ifndef __PORTER_H
12#define __PORTER_H
13
Vladimir Barinov60c04672015-02-14 01:06:13 +030014#include "rcar-gen2-common.h"
15
Marek Vasut7ee37d02018-02-16 01:33:27 +010016#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
17#define STACK_AREA_SIZE 0x00100000
Vladimir Barinov60c04672015-02-14 01:06:13 +030018#define LOW_LEVEL_MERAM_STACK \
19 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
20
21/* MEMORY */
22#define RCAR_GEN2_SDRAM_BASE 0x40000000
23#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
24#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
25
Vladimir Barinov60c04672015-02-14 01:06:13 +030026/* FLASH */
Vladimir Barinov60c04672015-02-14 01:06:13 +030027#define CONFIG_SPI_FLASH_QUAD
Vladimir Barinov60c04672015-02-14 01:06:13 +030028
29/* SH Ether */
Vladimir Barinov60c04672015-02-14 01:06:13 +030030#define CONFIG_SH_ETHER_USE_PORT 0
31#define CONFIG_SH_ETHER_PHY_ADDR 0x1
32#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
33#define CONFIG_SH_ETHER_CACHE_WRITEBACK
34#define CONFIG_SH_ETHER_CACHE_INVALIDATE
35#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
Vladimir Barinov60c04672015-02-14 01:06:13 +030036#define CONFIG_BITBANGMII
37#define CONFIG_BITBANGMII_MULTI
38
39/* Board Clock */
40#define RMOBILE_XTAL_CLK 20000000u
41#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
42#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
Vladimir Barinov60c04672015-02-14 01:06:13 +030043
44#define CONFIG_SYS_TMU_CLK_DIV 4
45
Marek Vasut7b8eeb42018-02-17 01:21:15 +010046#define CONFIG_EXTRA_ENV_SETTINGS \
47 "fdt_high=0xffffffff\0" \
48 "initrd_high=0xffffffff\0"
49
Marek Vasut7ee37d02018-02-16 01:33:27 +010050/* SPL support */
Marek Vasut0e592d02018-04-13 23:13:00 +020051#define CONFIG_SPL_TEXT_BASE 0xe6300000
Marek Vasut7ee37d02018-02-16 01:33:27 +010052#define CONFIG_SPL_STACK 0xe6340000
Marek Vasut0e592d02018-04-13 23:13:00 +020053#define CONFIG_SPL_MAX_SIZE 0x4000
Marek Vasut7ee37d02018-02-16 01:33:27 +010054#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
Marek Vasut0e592d02018-04-13 23:13:00 +020055#ifdef CONFIG_SPL_BUILD
Marek Vasut9a5483e2018-04-03 12:52:48 +020056#define CONFIG_CONS_SCIF0
57#define CONFIG_SH_SCIF_CLK_FREQ 65000000
58#endif
59
Vladimir Barinov60c04672015-02-14 01:06:13 +030060#endif /* __PORTER_H */