| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2004, Psyent Corporation <www.psyent.com> |
| 4 | * Scott McNutt <smcnutt@psyent.com> |
| wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| Thomas Chou | 57cfeb5 | 2014-08-25 17:09:07 +0800 | [diff] [blame] | 7 | #ifndef __ASM_NIOS2_H__ |
| 8 | #define __ASM_NIOS2_H__ |
| wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 9 | |
| 10 | /*------------------------------------------------------------------------ |
| 11 | * Control registers -- use with wrctl() & rdctl() |
| 12 | *----------------------------------------------------------------------*/ |
| 13 | #define CTL_STATUS 0 /* Processor status reg */ |
| 14 | #define CTL_ESTATUS 1 /* Exception status reg */ |
| 15 | #define CTL_BSTATUS 2 /* Break status reg */ |
| 16 | #define CTL_IENABLE 3 /* Interrut enable reg */ |
| 17 | #define CTL_IPENDING 4 /* Interrut pending reg */ |
| 18 | |
| 19 | /*------------------------------------------------------------------------ |
| 20 | * Access to control regs |
| 21 | *----------------------------------------------------------------------*/ |
| wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 22 | |
| Thomas Chou | 4f63bfb | 2012-11-09 14:29:15 +0800 | [diff] [blame] | 23 | #define rdctl(reg) __builtin_rdctl(reg) |
| 24 | #define wrctl(reg, val) __builtin_wrctl(reg, val) |
| wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 25 | |
| 26 | /*------------------------------------------------------------------------ |
| 27 | * Control reg bit masks |
| 28 | *----------------------------------------------------------------------*/ |
| 29 | #define STATUS_IE (1<<0) /* Interrupt enable */ |
| 30 | #define STATUS_U (1<<1) /* User-mode */ |
| 31 | |
| 32 | /*------------------------------------------------------------------------ |
| 33 | * Bit-31 Cache bypass -- only valid for data access. When data cache |
| 34 | * is not implemented, bit 31 is ignored for compatibility. |
| 35 | *----------------------------------------------------------------------*/ |
| 36 | #define CACHE_BYPASS(a) ((a) | 0x80000000) |
| 37 | #define CACHE_NO_BYPASS(a) ((a) & ~0x80000000) |
| 38 | |
| Thomas Chou | 57cfeb5 | 2014-08-25 17:09:07 +0800 | [diff] [blame] | 39 | #endif /* __ASM_NIOS2_H__ */ |