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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Peter Tysera7c93102008-12-17 16:36:22 -06002/*
3 * Copyright 2008 Extreme Engineering Solutions, Inc.
Peter Tysera7c93102008-12-17 16:36:22 -06004 */
5
6#ifndef __DS4510_H_
7#define __DS4510_H_
8
9/* General defines */
10#define DS4510_NUM_IO 0x04
11#define DS4510_IO_MASK ((1 << DS4510_NUM_IO) - 1)
12#define DS4510_EEPROM_PAGE_WRITE_DELAY_MS 20
13
14/* EEPROM from 0x00 - 0x39 */
15#define DS4510_EEPROM 0x00
16#define DS4510_EEPROM_SIZE 0x40
17#define DS4510_EEPROM_PAGE_SIZE 0x08
18#define DS4510_EEPROM_PAGE_OFFSET(x) ((x) & (DS4510_EEPROM_PAGE_SIZE - 1))
19
20/* SEEPROM from 0xf0 - 0xf7 */
21#define DS4510_SEEPROM 0xf0
22#define DS4510_SEEPROM_SIZE 0x08
23
24/* Registers overlapping SEEPROM from 0xf0 - 0xf7 */
25#define DS4510_PULLUP 0xF0
26#define DS4510_PULLUP_DIS 0x00
27#define DS4510_PULLUP_EN 0x01
28#define DS4510_RSTDELAY 0xF1
29#define DS4510_RSTDELAY_MASK 0x03
30#define DS4510_RSTDELAY_125 0x00
31#define DS4510_RSTDELAY_250 0x01
32#define DS4510_RSTDELAY_500 0x02
33#define DS4510_RSTDELAY_1000 0x03
34#define DS4510_IO3 0xF4
35#define DS4510_IO2 0xF5
36#define DS4510_IO1 0xF6
37#define DS4510_IO0 0xF7
38
39/* Status configuration registers from 0xf8 - 0xf9*/
40#define DS4510_IO_STATUS 0xF8
41#define DS4510_CFG 0xF9
42#define DS4510_CFG_READY 0x80
43#define DS4510_CFG_TRIP_POINT 0x40
44#define DS4510_CFG_RESET 0x20
45#define DS4510_CFG_SEE 0x10
46#define DS4510_CFG_SWRST 0x08
47
48/* SRAM from 0xfa - 0xff */
49#define DS4510_SRAM 0xfa
50#define DS4510_SRAM_SIZE 0x06
51
Peter Tysera7c93102008-12-17 16:36:22 -060052#endif /* __DS4510_H_ */