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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Mateusz Kulikowski142a20c2016-03-31 23:12:14 +02002/*
3 * Qualcomm UART driver
4 *
5 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
6 *
7 * UART will work in Data Mover mode.
8 * Based on Linux driver.
Mateusz Kulikowski142a20c2016-03-31 23:12:14 +02009 */
10
11#include <common.h>
12#include <clk.h>
13#include <dm.h>
14#include <errno.h>
15#include <serial.h>
16#include <watchdog.h>
17#include <asm/io.h>
18#include <linux/compiler.h>
19
20/* Serial registers - this driver works in uartdm mode*/
21
22#define UARTDM_DMRX 0x34 /* Max RX transfer length */
23#define UARTDM_NCF_TX 0x40 /* Number of chars to TX */
24
25#define UARTDM_RXFS 0x50 /* RX channel status register */
26#define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */
27#define UARTDM_RXFS_BUF_MASK 0x7
28
29#define UARTDM_SR 0xA4 /* Status register */
30#define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
31#define UARTDM_SR_TX_EMPTY (1 << 3) /* Transmitter underrun */
32#define UARTDM_SR_UART_OVERRUN (1 << 4) /* Receive overrun */
33
34#define UARTDM_CR 0xA8 /* Command register */
35#define UARTDM_CR_CMD_RESET_ERR (3 << 4) /* Clear overrun error */
36#define UARTDM_CR_CMD_RESET_STALE_INT (8 << 4) /* Clears stale irq */
37#define UARTDM_CR_CMD_RESET_TX_READY (3 << 8) /* Clears TX Ready irq*/
38#define UARTDM_CR_CMD_FORCE_STALE (4 << 8) /* Causes stale event */
39#define UARTDM_CR_CMD_STALE_EVENT_DISABLE (6 << 8) /* Disable stale event */
40
41#define UARTDM_IMR 0xB0 /* Interrupt mask register */
42#define UARTDM_ISR 0xB4 /* Interrupt status register */
43#define UARTDM_ISR_TX_READY 0x80 /* TX FIFO empty */
44
45#define UARTDM_TF 0x100 /* UART Transmit FIFO register */
46#define UARTDM_RF 0x140 /* UART Receive FIFO register */
47
48
49DECLARE_GLOBAL_DATA_PTR;
50
51struct msm_serial_data {
52 phys_addr_t base;
53 unsigned chars_cnt; /* number of buffered chars */
54 uint32_t chars_buf; /* buffered chars */
55};
56
57static int msm_serial_fetch(struct udevice *dev)
58{
59 struct msm_serial_data *priv = dev_get_priv(dev);
60 unsigned sr;
61
62 if (priv->chars_cnt)
63 return priv->chars_cnt;
64
65 /* Clear error in case of buffer overrun */
66 if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
67 writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
68
69 /* We need to fetch new character */
70 sr = readl(priv->base + UARTDM_SR);
71
72 if (sr & UARTDM_SR_RX_READY) {
73 /* There are at least 4 bytes in fifo */
74 priv->chars_buf = readl(priv->base + UARTDM_RF);
75 priv->chars_cnt = 4;
76 } else {
77 /* Check if there is anything in fifo */
78 priv->chars_cnt = readl(priv->base + UARTDM_RXFS);
79 /* Extract number of characters in UART packing buffer*/
80 priv->chars_cnt = (priv->chars_cnt >>
81 UARTDM_RXFS_BUF_SHIFT) &
82 UARTDM_RXFS_BUF_MASK;
83 if (!priv->chars_cnt)
84 return 0;
85
86 /* There is at least one charcter, move it to fifo */
87 writel(UARTDM_CR_CMD_FORCE_STALE,
88 priv->base + UARTDM_CR);
89
90 priv->chars_buf = readl(priv->base + UARTDM_RF);
91 writel(UARTDM_CR_CMD_RESET_STALE_INT,
92 priv->base + UARTDM_CR);
93 writel(0x7, priv->base + UARTDM_DMRX);
94 }
95
96 return priv->chars_cnt;
97}
98
99static int msm_serial_getc(struct udevice *dev)
100{
101 struct msm_serial_data *priv = dev_get_priv(dev);
102 char c;
103
104 if (!msm_serial_fetch(dev))
105 return -EAGAIN;
106
107 c = priv->chars_buf & 0xFF;
108 priv->chars_buf >>= 8;
109 priv->chars_cnt--;
110
111 return c;
112}
113
114static int msm_serial_putc(struct udevice *dev, const char ch)
115{
116 struct msm_serial_data *priv = dev_get_priv(dev);
117
118 if (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
119 !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
120 return -EAGAIN;
121
122 writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
123
124 writel(1, priv->base + UARTDM_NCF_TX);
125 writel(ch, priv->base + UARTDM_TF);
126
127 return 0;
128}
129
130static int msm_serial_pending(struct udevice *dev, bool input)
131{
132 if (input) {
133 if (msm_serial_fetch(dev))
134 return 1;
135 }
136
137 return 0;
138}
139
140static const struct dm_serial_ops msm_serial_ops = {
141 .putc = msm_serial_putc,
142 .pending = msm_serial_pending,
143 .getc = msm_serial_getc,
144};
145
146static int msm_uart_clk_init(struct udevice *dev)
147{
Simon Glasse160f7d2017-01-17 16:52:55 -0700148 uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
Mateusz Kulikowski142a20c2016-03-31 23:12:14 +0200149 "clock-frequency", 115200);
150 uint clkd[2]; /* clk_id and clk_no */
151 int clk_offset;
Stephen Warren135aa952016-06-17 09:44:00 -0600152 struct udevice *clk_dev;
153 struct clk clk;
Mateusz Kulikowski142a20c2016-03-31 23:12:14 +0200154 int ret;
155
Simon Glasse160f7d2017-01-17 16:52:55 -0700156 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "clock",
157 clkd, 2);
Mateusz Kulikowski142a20c2016-03-31 23:12:14 +0200158 if (ret)
159 return ret;
160
161 clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
162 if (clk_offset < 0)
163 return clk_offset;
164
Stephen Warren135aa952016-06-17 09:44:00 -0600165 ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
Mateusz Kulikowski142a20c2016-03-31 23:12:14 +0200166 if (ret)
167 return ret;
168
Stephen Warren135aa952016-06-17 09:44:00 -0600169 clk.id = clkd[1];
170 ret = clk_request(clk_dev, &clk);
171 if (ret < 0)
172 return ret;
173
174 ret = clk_set_rate(&clk, clk_rate);
175 clk_free(&clk);
Mateusz Kulikowski142a20c2016-03-31 23:12:14 +0200176 if (ret < 0)
177 return ret;
178
179 return 0;
180}
181
182static int msm_serial_probe(struct udevice *dev)
183{
184 struct msm_serial_data *priv = dev_get_priv(dev);
185
186 msm_uart_clk_init(dev); /* Ignore return value and hope clock was
187 properly initialized by earlier loaders */
188
189 if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
190 writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
191
192 writel(0, priv->base + UARTDM_IMR);
193 writel(UARTDM_CR_CMD_STALE_EVENT_DISABLE, priv->base + UARTDM_CR);
194 msm_serial_fetch(dev);
195
196 return 0;
197}
198
199static int msm_serial_ofdata_to_platdata(struct udevice *dev)
200{
201 struct msm_serial_data *priv = dev_get_priv(dev);
202
Simon Glassa821c4a2017-05-17 17:18:05 -0600203 priv->base = devfdt_get_addr(dev);
Mateusz Kulikowski142a20c2016-03-31 23:12:14 +0200204 if (priv->base == FDT_ADDR_T_NONE)
205 return -EINVAL;
206
207 return 0;
208}
209
210static const struct udevice_id msm_serial_ids[] = {
211 { .compatible = "qcom,msm-uartdm-v1.4" },
212 { }
213};
214
215U_BOOT_DRIVER(serial_msm) = {
216 .name = "serial_msm",
217 .id = UCLASS_SERIAL,
218 .of_match = msm_serial_ids,
219 .ofdata_to_platdata = msm_serial_ofdata_to_platdata,
220 .priv_auto_alloc_size = sizeof(struct msm_serial_data),
221 .probe = msm_serial_probe,
222 .ops = &msm_serial_ops,
223};