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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Jon Loeliger0cde4b02007-04-11 16:50:57 -05002/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06003 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
Jon Loeliger0cde4b02007-04-11 16:50:57 -05004 */
5
6/*
7 * mpc8544ds board configuration file
8 *
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Ed Swarthout837f1ba2007-07-27 01:50:51 -050013#define CONFIG_PCI1 1 /* PCI controller 1 */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040014#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
15#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
16#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
Ed Swarthout837f1ba2007-07-27 01:50:51 -050017#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000018#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala8ff3de62007-12-07 12:17:34 -060019#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050020#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050021
Jon Loeliger0cde4b02007-04-11 16:50:57 -050022#define CONFIG_ENV_OVERWRITE
Ed Swarthout837f1ba2007-07-27 01:50:51 -050023#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050024
Jon Loeliger0cde4b02007-04-11 16:50:57 -050025#ifndef __ASSEMBLY__
26extern unsigned long get_board_sys_clk(unsigned long dummy);
27#endif
28#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
29
30/*
31 * These can be toggled for performance analysis, otherwise use default.
32 */
Ed Swarthout837f1ba2007-07-27 01:50:51 -050033#define CONFIG_L2_CACHE /* toggle L2 cache */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050034#define CONFIG_BTB /* toggle branch predition */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050035
36/*
37 * Only possible on E500 Version 2 or newer cores.
38 */
39#define CONFIG_ENABLE_36BIT_PHYS 1
40
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
42#define CONFIG_SYS_MEMTEST_END 0x00400000
Jon Loeliger0cde4b02007-04-11 16:50:57 -050043
Timur Tabie46fedf2011-08-04 18:03:41 -050044#define CONFIG_SYS_CCSRBAR 0xe0000000
45#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Jon Loeliger0cde4b02007-04-11 16:50:57 -050046
Kumar Gala1167a2f2008-08-26 08:02:30 -050047/* DDR Setup */
Kumar Gala1167a2f2008-08-26 08:02:30 -050048#undef CONFIG_FSL_DDR_INTERACTIVE
49#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
50#define CONFIG_DDR_SPD
Jon Loeliger0cde4b02007-04-11 16:50:57 -050051
Dave Liu9b0ad1b2008-10-28 17:53:38 +080052#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Kumar Gala1167a2f2008-08-26 08:02:30 -050053#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
54
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
56#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala1167a2f2008-08-26 08:02:30 -050057#define CONFIG_VERY_BIG_RAM
58
Kumar Gala1167a2f2008-08-26 08:02:30 -050059#define CONFIG_DIMM_SLOTS_PER_CTLR 1
60#define CONFIG_CHIP_SELECTS_PER_CTRL 2
61
62/* I2C addresses of SPD EEPROMs */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050063#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
64
Kumar Gala1167a2f2008-08-26 08:02:30 -050065/* Make sure required options are set */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050066#ifndef CONFIG_SPD_EEPROM
67#error ("CONFIG_SPD_EEPROM is required")
68#endif
69
70#undef CONFIG_CLOCKS_IN_MHZ
71
72/*
73 * Memory map
74 *
75 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
76 *
77 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
78 *
79 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
80 *
81 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
82 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
83 *
84 * Localbus cacheable
85 *
86 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
87 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
88 *
89 * Localbus non-cacheable
90 *
91 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
92 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
93 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
94 *
95 */
96
97/*
98 * Local Bus Definitions
99 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_BR0_PRELIM 0xff801001
105#define CONFIG_SYS_BR1_PRELIM 0xfe801001
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_OR0_PRELIM 0xff806e65
108#define CONFIG_SYS_OR1_PRELIM 0xff806e65
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_FLASH_QUIET_TEST
113#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
114#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
115#undef CONFIG_SYS_FLASH_CHECKSUM
116#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
117#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala81e56e92008-06-09 18:55:38 -0500118#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500119
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200120#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500121
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200122#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_FLASH_CFI
124#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
129#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
132#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500133
Kim Phillips7608d752007-08-21 17:00:17 -0500134#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500135#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
136#define PIXIS_ID 0x0 /* Board ID at offset 0 */
137#define PIXIS_VER 0x1 /* Board version at offset 1 */
138#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
139#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
140#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
141 * register */
142#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
143#define PIXIS_VCTL 0x10 /* VELA Control Register */
144#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
145#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
146#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500147#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
148#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500149#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
150#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
151#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
152#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Andy Fleming5a8a1632008-08-31 16:33:30 -0500153#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
Andy Fleming5a8a1632008-08-31 16:33:30 -0500155#define PIXIS_VSPEED2_TSEC1SER 0x2
156#define PIXIS_VSPEED2_TSEC3SER 0x1
157#define PIXIS_VCFGEN1_TSEC1SER 0x20
158#define PIXIS_VCFGEN1_TSEC3SER 0x40
Liu Yubff188b2008-10-10 11:40:58 +0800159#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
160#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_INIT_RAM_LOCK 1
163#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200164#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500165
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200166#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
170#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500171
172/* Serial Port - controlled on board with jumper J8
173 * open - index 2
174 * shorted - index 1
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_NS16550_SERIAL
177#define CONFIG_SYS_NS16550_REG_SIZE 1
178#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500181 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
184#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500185
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500186/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200187#define CONFIG_SYS_I2C
188#define CONFIG_SYS_I2C_FSL
189#define CONFIG_SYS_FSL_I2C_SPEED 400000
190#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
Benjamin Kamath7f25fdc2016-06-29 16:44:38 -0700191#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
Heiko Schocher00f792e2012-10-24 13:48:22 +0200192#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500194
195/*
196 * General PCI
197 * Memory space is mapped 1-1, but I/O space must start from 0.
198 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600199#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600201#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500203
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600204#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600205#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600206#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600208#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600209#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
211#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500212
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500213/* controller 2, Slot 1, tgtid 1, Base address 9000 */
Kumar Gala64a16862010-12-17 06:01:24 -0600214#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600215#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600216#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600217#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600219#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600220#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
222#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500223
224/* controller 1, Slot 2,tgtid 2, Base address a000 */
Kumar Gala64a16862010-12-17 06:01:24 -0600225#define CONFIG_SYS_PCIE1_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600226#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600227#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600228#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600230#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600231#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
233#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500234
235/* controller 3, direct to uli, tgtid 3, Base address b000 */
Kumar Gala64a16862010-12-17 06:01:24 -0600236#define CONFIG_SYS_PCIE3_NAME "ULI"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600237#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600238#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600239#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600241#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
Kumar Gala5f91ef62008-12-02 16:08:37 -0600242#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
244#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600245#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
Kumar Gala10795f42008-12-02 16:08:36 -0600246#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600247#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500249
250#if defined(CONFIG_PCI)
251
Kumar Gala630d9bf2008-07-14 14:07:03 -0500252/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600253#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
Kumar Gala630d9bf2008-07-14 14:07:03 -0500254
255/*PCI video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600256/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
Kumar Gala630d9bf2008-07-14 14:07:03 -0500257
258/* video */
Kumar Gala630d9bf2008-07-14 14:07:03 -0500259
260#if defined(CONFIG_VIDEO)
261#define CONFIG_BIOSEMU
Kumar Gala630d9bf2008-07-14 14:07:03 -0500262#define CONFIG_ATI_RADEON_FB
263#define CONFIG_VIDEO_LOGO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala630d9bf2008-07-14 14:07:03 -0500265#endif
266
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500267#undef CONFIG_EEPRO100
268#undef CONFIG_TULIP
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500269
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500270#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600271 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
272 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500273 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
274#endif
275
276#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500277
278#ifdef CONFIG_SCSI_AHCI
279#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
281#define CONFIG_SYS_SCSI_MAX_LUN 1
282#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
283#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500284#endif /* SCSCI */
285
286#endif /* CONFIG_PCI */
287
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500288#if defined(CONFIG_TSEC_ENET)
289
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500290#define CONFIG_MII 1 /* MII PHY management */
291#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
Kim Phillips255a35772007-05-16 16:52:19 -0500292#define CONFIG_TSEC1 1
293#define CONFIG_TSEC1_NAME "eTSEC1"
294#define CONFIG_TSEC3 1
295#define CONFIG_TSEC3_NAME "eTSEC3"
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500296
Liu Yubff188b2008-10-10 11:40:58 +0800297#define CONFIG_PIXIS_SGMII_CMD
Andy Fleming652f7c22008-08-31 16:33:28 -0500298#define CONFIG_FSL_SGMII_RISER 1
299#define SGMII_RISER_PHY_OFFSET 0x1c
300
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500301#define TSEC1_PHY_ADDR 0
302#define TSEC3_PHY_ADDR 1
303
Andy Fleming3a790132007-08-15 20:03:25 -0500304#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
305#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
306
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500307#define TSEC1_PHYIDX 0
308#define TSEC3_PHYIDX 0
309
310#define CONFIG_ETHPRIME "eTSEC1"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500311#endif /* CONFIG_TSEC_ENET */
312
313/*
314 * Environment
315 */
York Sun109f5a22017-06-07 10:12:56 -0700316#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200318#define CONFIG_ENV_ADDR 0xfff80000
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500319#else
York Sun109f5a22017-06-07 10:12:56 -0700320#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500321#endif
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200322#define CONFIG_ENV_SIZE 0x2000
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500323
324#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500326
Jon Loeliger2835e512007-06-13 13:22:08 -0500327/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500328 * BOOTP options
329 */
330#define CONFIG_BOOTP_BOOTFILESIZE
Jon Loeliger659e2f62007-07-10 09:10:49 -0500331
Jon Loeliger659e2f62007-07-10 09:10:49 -0500332/*
Hongtao Jia86a194b2012-12-20 19:39:53 +0000333 * USB
334 */
Hongtao Jia86a194b2012-12-20 19:39:53 +0000335
Tom Rini8850c5d2017-05-12 22:33:27 -0400336#ifdef CONFIG_USB_EHCI_HCD
Hongtao Jia86a194b2012-12-20 19:39:53 +0000337#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Hongtao Jia86a194b2012-12-20 19:39:53 +0000338#define CONFIG_PCI_EHCI_DEVICE 0
339#endif
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500340
341#undef CONFIG_WATCHDOG /* watchdog disabled */
342
343/*
344 * Miscellaneous configurable options
345 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500347
348/*
349 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500350 * have to be in the first 64 MB of memory, since this is
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500351 * the maximum mapped by the Linux kernel during initialization.
352 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500353#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
354#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500355
Jon Loeliger2835e512007-06-13 13:22:08 -0500356#if defined(CONFIG_CMD_KGDB)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500357#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500358#endif
359
360/*
361 * Environment Configuration
362 */
363
364/* The mac addresses for all ethernet interface */
365#if defined(CONFIG_TSEC_ENET)
Kumar Galaea5877e2007-08-16 11:01:21 -0500366#define CONFIG_HAS_ETH0
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500367#define CONFIG_HAS_ETH1
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500368#endif
369
370#define CONFIG_IPADDR 192.168.1.251
371
Mario Six5bc05432018-03-28 14:38:20 +0200372#define CONFIG_HOSTNAME "8544ds_unknown"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000373#define CONFIG_ROOTPATH "/nfs/mpc85xx"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000374#define CONFIG_BOOTFILE "8544ds/uImage.uboot"
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500375#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500376
Kumar Gala50c03c82007-11-27 22:42:34 -0600377#define CONFIG_SERVERIP 192.168.1.1
378#define CONFIG_GATEWAYIP 192.168.1.1
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500379#define CONFIG_NETMASK 255.255.0.0
380
381#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
382
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500383#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200384"netdev=eth0\0" \
385"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
386"tftpflash=tftpboot $loadaddr $uboot; " \
387 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
388 " +$filesize; " \
389 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
390 " +$filesize; " \
391 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
392 " $filesize; " \
393 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
394 " +$filesize; " \
395 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
396 " $filesize\0" \
397"consoledev=ttyS0\0" \
398"ramdiskaddr=2000000\0" \
399"ramdiskfile=8544ds/ramdisk.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500400"fdtaddr=1e00000\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200401"fdtfile=8544ds/mpc8544ds.dtb\0" \
402"bdev=sda3\0"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500403
404#define CONFIG_NFSBOOTCOMMAND \
405 "setenv bootargs root=/dev/nfs rw " \
406 "nfsroot=$serverip:$rootpath " \
407 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
408 "console=$consoledev,$baudrate $othbootargs;" \
409 "tftp $loadaddr $bootfile;" \
Kumar Gala50c03c82007-11-27 22:42:34 -0600410 "tftp $fdtaddr $fdtfile;" \
411 "bootm $loadaddr - $fdtaddr"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500412
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500413#define CONFIG_RAMBOOTCOMMAND \
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500414 "setenv bootargs root=/dev/ram rw " \
415 "console=$consoledev,$baudrate $othbootargs;" \
416 "tftp $ramdiskaddr $ramdiskfile;" \
417 "tftp $loadaddr $bootfile;" \
Kumar Gala50c03c82007-11-27 22:42:34 -0600418 "tftp $fdtaddr $fdtfile;" \
419 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500420
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500421#define CONFIG_BOOTCOMMAND \
422 "setenv bootargs root=/dev/$bdev rw " \
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500423 "console=$consoledev,$baudrate $othbootargs;" \
424 "tftp $loadaddr $bootfile;" \
Kumar Gala50c03c82007-11-27 22:42:34 -0600425 "tftp $fdtaddr $fdtfile;" \
426 "bootm $loadaddr - $fdtaddr"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500427
428#endif /* __CONFIG_H */