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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Yusuke Godac133c1f2008-03-11 12:55:12 +09002/*
3 * Configuation settings for the Renesas R7780MP board
4 *
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +09005 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Yusuke Godac133c1f2008-03-11 12:55:12 +09006 * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
Yusuke Godac133c1f2008-03-11 12:55:12 +09007 */
8
9#ifndef __R7780RP_H
10#define __R7780RP_H
11
Yusuke Godac133c1f2008-03-11 12:55:12 +090012#define CONFIG_CPU_SH7780 1
13#define CONFIG_R7780MP 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020014#define CONFIG_SYS_R7780MP_OLD_FLASH 1
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090015#define __LITTLE_ENDIAN__ 1
Yusuke Godac133c1f2008-03-11 12:55:12 +090016
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020017#define CONFIG_DISPLAY_BOARDINFO
18
Yusuke Godac133c1f2008-03-11 12:55:12 +090019#define CONFIG_CONS_SCIF0 1
20
Yusuke Godac133c1f2008-03-11 12:55:12 +090021#define CONFIG_ENV_OVERWRITE 1
22
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023#define CONFIG_SYS_SDRAM_BASE (0x08000000)
24#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +090025
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#define CONFIG_SYS_PBSIZE 256
Yusuke Godac133c1f2008-03-11 12:55:12 +090027
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020028#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +020029#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
Yusuke Godac133c1f2008-03-11 12:55:12 +090030
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090031/* Flash board support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#define CONFIG_SYS_FLASH_BASE (0xA0000000)
33#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090034/* NOR Flash (S29PL127J60TFI130) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
36# define CONFIG_SYS_MAX_FLASH_BANKS (2)
37# define CONFIG_SYS_MAX_FLASH_SECT 270
38# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
39 CONFIG_SYS_FLASH_BASE + 0x100000,\
40 CONFIG_SYS_FLASH_BASE + 0x400000,\
41 CONFIG_SYS_FLASH_BASE + 0x700000, }
42#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090043/* NOR Flash (Spantion S29GL256P) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044# define CONFIG_SYS_MAX_FLASH_BANKS (1)
45# define CONFIG_SYS_MAX_FLASH_SECT 256
46# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
47#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
Yusuke Godac133c1f2008-03-11 12:55:12 +090048
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +090050/* Address of u-boot image in Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
52#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +090053/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_MALLOC_LEN (1204 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +090055
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
57#define CONFIG_SYS_RX_ETH_BUFFER (8)
Yusuke Godac133c1f2008-03-11 12:55:12 +090058
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020060#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
62#undef CONFIG_SYS_FLASH_QUIET_TEST
Yusuke Godac133c1f2008-03-11 12:55:12 +090063/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_FLASH_EMPTY_INFO
Yusuke Godac133c1f2008-03-11 12:55:12 +090065
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020066#define CONFIG_ENV_SECT_SIZE (256 * 1024)
67#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
69#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
70#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Yusuke Godac133c1f2008-03-11 12:55:12 +090071
72/* Board Clock */
73#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090074#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
75#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +020076#define CONFIG_SYS_TMU_CLK_DIV 4
Yusuke Godac133c1f2008-03-11 12:55:12 +090077
78/* PCI Controller */
79#if defined(CONFIG_CMD_PCI)
Yusuke Godac133c1f2008-03-11 12:55:12 +090080#define CONFIG_SH4_PCI
Nobuhiro Iwamatsuab8f4d42008-03-24 02:11:26 +090081#define CONFIG_SH7780_PCI
Yoshihiro Shimoda06b18162009-02-25 14:26:42 +090082#define CONFIG_SH7780_PCI_LSR 0x07f00001
83#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
84#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
Yusuke Godac133c1f2008-03-11 12:55:12 +090085#define CONFIG_PCI_SCAN_SHOW 1
Yusuke Godac133c1f2008-03-11 12:55:12 +090086#define __mem_pci
87
88#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
89#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
90#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
91
92#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
93#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
94#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
Nobuhiro Iwamatsu04366d02009-07-08 11:42:19 +090095#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
96#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
97#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
Yusuke Godac133c1f2008-03-11 12:55:12 +090098#endif /* CONFIG_CMD_PCI */
99
100#if defined(CONFIG_CMD_NET)
Marcel Ziswilerc7c1dbb2009-09-09 21:09:00 +0200101/* AX88796L Support(NE2000 base chip) */
Yusuke Godac133c1f2008-03-11 12:55:12 +0900102#define CONFIG_DRIVER_AX88796L
103#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
104#endif
105
106/* Compact flash Support */
Simon Glassfc843a02017-05-17 03:25:30 -0600107#if defined(CONFIG_IDE)
Yusuke Godac133c1f2008-03-11 12:55:12 +0900108#define CONFIG_IDE_RESET 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_PIO_MODE 1
110#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
111#define CONFIG_SYS_IDE_MAXDEVICE 1
112#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
113#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
114#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
115#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
116#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
Albert Aribaudf2a37fc2010-08-08 05:17:05 +0530117#define CONFIG_IDE_SWAP_IO
Simon Glassfc843a02017-05-17 03:25:30 -0600118#endif /* CONFIG_IDE */
Yusuke Godac133c1f2008-03-11 12:55:12 +0900119
120#endif /* __R7780RP_H */