blob: 080b4055cfbfb283db6aa650cbdd2815d09bb7bc [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +09002/*
3 * Configuation settings for the sh7753evb board
4 *
5 * Copyright (C) 2012 Renesas Solutions Corp.
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +09006 */
7
8#ifndef __SH7753EVB_H
9#define __SH7753EVB_H
10
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090011#define CONFIG_CPU_SH7753 1
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090012
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020013#define CONFIG_DISPLAY_BOARDINFO
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090014#undef CONFIG_SHOW_BOOT_PROGRESS
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090015
16/* MEMORY */
17#define SH7753EVB_SDRAM_BASE (0x40000000)
18#define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024)
19
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090020#define CONFIG_SYS_PBSIZE 256
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090021#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
22
23/* SCIF */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090024#define CONFIG_CONS_SCIF2 1
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090025
26#define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE)
27#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
28 480 * 1024 * 1024)
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090029#undef CONFIG_SYS_MEMTEST_SCRATCH
30#undef CONFIG_SYS_LOADS_BAUD_CHANGE
31
32#define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE)
33#define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE)
34#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
35 128 * 1024 * 1024)
36
37#define CONFIG_SYS_MONITOR_BASE 0x00000000
38#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
39#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
40#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
41
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090042/* Ether */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090043#define CONFIG_SH_ETHER_USE_PORT 0
44#define CONFIG_SH_ETHER_PHY_ADDR 18
45#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
46#define CONFIG_SH_ETHER_USE_GETHER 1
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090047#define CONFIG_BITBANGMII
48#define CONFIG_BITBANGMII_MULTI
49#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
50#define CONFIG_PHY_VITESSE
51
52#define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000
53#define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024)
54#define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI
55#define SH7753EVB_ETHERNET_MAC_SIZE 17
56#define SH7753EVB_ETHERNET_NUM_CH 2
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090057
58/* SPI */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090059#define CONFIG_SH_SPI_BASE 0xfe002000
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090060
61/* MMCIF */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090062#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
63#define CONFIG_SH_MMCIF_CLK 48000000
64
65/* ENV setting */
66#define CONFIG_ENV_IS_EMBEDDED
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090067#define CONFIG_ENV_SECT_SIZE (64 * 1024)
68#define CONFIG_ENV_ADDR (0x00080000)
69#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
70#define CONFIG_ENV_OVERWRITE 1
71#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
72#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
73#define CONFIG_EXTRA_ENV_SETTINGS \
74 "netboot=bootp; bootm\0"
75
76/* Board Clock */
77#define CONFIG_SYS_CLK_FREQ 48000000
78#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
79#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
80#define CONFIG_SYS_TMU_CLK_DIV 4
81#endif /* __SH7753EVB_H */