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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +09002/*
Nobuhiro Iwamatsua9720892011-01-06 12:38:01 +09003 * Configuation settings for shmin (T-SH7706LAN, T-SH7706LSR)
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +09004 *
Nobuhiro Iwamatsua9720892011-01-06 12:38:01 +09005 * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +09006 */
7
8#ifndef __SHMIN_H
9#define __SHMIN_H
10
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090011#define CONFIG_CPU_SH7706 1
Nobuhiro Iwamatsua9720892011-01-06 12:38:01 +090012/* T-SH7706LAN */
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090013#define CONFIG_SHMIN 1
Nobuhiro Iwamatsua9720892011-01-06 12:38:01 +090014/* T-SH7706LSR*/
15/* #define CONFIG_T_SH7706LSR 1 */
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090016
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010017/*
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090018 * This board has original boot loader. If you write u-boot to 0x0,
19 * you should set undef.
20 */
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090021#undef CONFIG_SHOW_BOOT_PROGRESS
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020022#define CONFIG_DISPLAY_BOARDINFO
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090023
24/* system */
25#define SHMIN_SDRAM_BASE (0x8C000000)
26#define SHMIN_FLASH_BASE_1 (0xA0000000)
27
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090028#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090029/* List of legal baudrate settings for this board */
Nobuhiro Iwamatsua9720892011-01-06 12:38:01 +090030#define CONFIG_SYS_BAUDRATE_TABLE { 9600,14400,19200,38400,57600,115200 }
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090031
32/* SCIF */
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090033#define CONFIG_CONS_SCIF0 1
34
35/* memory */
36#define CONFIG_SYS_SDRAM_BASE SHMIN_SDRAM_BASE
37#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
38#define CONFIG_SYS_MEMTEST_START SHMIN_SDRAM_BASE
39#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - (256 * 1024))
40
41#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1 * 1024 * 1024)
42#define CONFIG_SYS_MONITOR_BASE (SHMIN_FLASH_BASE_1 + CONFIG_ENV_SECT_SIZE)
43#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
44#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090045#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
46
47/* FLASH */
48#define CONFIG_SYS_FLASH_CFI
49#define CONFIG_FLASH_CFI_DRIVER
50#undef CONFIG_SYS_FLASH_QUIET_TEST
51#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
52#define CONFIG_SYS_FLASH_BASE SHMIN_FLASH_BASE_1
53#define CONFIG_SYS_MAX_FLASH_SECT 11
54#define CONFIG_SYS_MAX_FLASH_BANKS 1
55
56#define CONFIG_FLASH_CFI_LEGACY
57#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_FLASH_BASE
58#define CONFIG_SYS_ATMEL_TOTALSECT CONFIG_SYS_MAX_FLASH_SECT
59#define CONFIG_SYS_ATMEL_REGION 4
60#define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
61#define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
62
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090063#define CONFIG_ENV_SECT_SIZE (64 * 1024)
64#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Nobuhiro Iwamatsua9720892011-01-06 12:38:01 +090065
66#ifdef CONFIG_T_SH7706LSR
67#define CONFIG_ENV_ADDR (SHMIN_FLASH_BASE_1 + 70000)
68#else
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090069#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Nobuhiro Iwamatsua9720892011-01-06 12:38:01 +090070#endif
71
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090072#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
73#define CONFIG_SYS_FLASH_WRITE_TOUT 500
74
75/* Board Clock */
Nobuhiro Iwamatsua9720892011-01-06 12:38:01 +090076#ifdef CONFIG_T_SH7706LSR
77#define CONFIG_SYS_CLK_FREQ 40000000
78#else
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090079#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsua9720892011-01-06 12:38:01 +090080#endif /* CONFIG_T_SH7706LSR */
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090081#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
82#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090083#define CONFIG_SYS_TMU_CLK_DIV 4
Nobuhiro Iwamatsu6b7c0f52010-10-25 03:12:24 +090084
85/* Network device */
86#define CONFIG_DRIVER_NE2000
87#define CONFIG_DRIVER_NE2000_BASE (0xb0000300)
88
89#endif /* __SHMIN_H */