blob: eab0ef213ac0e991f580136ac2e41d4c580616aa [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Vladimir Barinov21871132015-07-20 20:49:59 +03002/*
3 * include/configs/stout.h
4 * This file is Stout board configuration.
5 *
6 * Copyright (C) 2015 Renesas Electronics Europe GmbH
7 * Copyright (C) 2015 Renesas Electronics Corporation
8 * Copyright (C) 2015 Cogent Embedded, Inc.
Vladimir Barinov21871132015-07-20 20:49:59 +03009 */
10
11#ifndef __STOUT_H
12#define __STOUT_H
13
Vladimir Barinov21871132015-07-20 20:49:59 +030014#include "rcar-gen2-common.h"
15
Marek Vasutec7113f2018-04-12 15:23:46 +020016#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
17#define STACK_AREA_SIZE 0x00100000
18#define LOW_LEVEL_MERAM_STACK \
Vladimir Barinov21871132015-07-20 20:49:59 +030019 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
20
21/* MEMORY */
22#define RCAR_GEN2_SDRAM_BASE 0x40000000
23#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
24#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
25
26/* SCIF */
Vladimir Barinov21871132015-07-20 20:49:59 +030027#define CONFIG_SCIF_A
28
29/* SPI */
Vladimir Barinov21871132015-07-20 20:49:59 +030030#define CONFIG_SPI_FLASH_QUAD
Vladimir Barinov21871132015-07-20 20:49:59 +030031
32/* SH Ether */
Vladimir Barinov21871132015-07-20 20:49:59 +030033#define CONFIG_SH_ETHER_USE_PORT 0
34#define CONFIG_SH_ETHER_PHY_ADDR 0x1
35#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
Vladimir Barinov21871132015-07-20 20:49:59 +030036#define CONFIG_SH_ETHER_CACHE_WRITEBACK
37#define CONFIG_SH_ETHER_CACHE_INVALIDATE
Marek Vasutec7113f2018-04-12 15:23:46 +020038#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
Vladimir Barinov21871132015-07-20 20:49:59 +030039#define CONFIG_BITBANGMII
40#define CONFIG_BITBANGMII_MULTI
41
Vladimir Barinov21871132015-07-20 20:49:59 +030042/* Board Clock */
43#define RMOBILE_XTAL_CLK 20000000u
44#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
Marek Vasutec7113f2018-04-12 15:23:46 +020045#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
Vladimir Barinov21871132015-07-20 20:49:59 +030046
47#define CONFIG_SYS_TMU_CLK_DIV 4
48
Marek Vasutec7113f2018-04-12 15:23:46 +020049#define CONFIG_EXTRA_ENV_SETTINGS \
50 "fdt_high=0xffffffff\0" \
51 "initrd_high=0xffffffff\0"
Vladimir Barinov21871132015-07-20 20:49:59 +030052
Marek Vasutec7113f2018-04-12 15:23:46 +020053/* SPL support */
Marek Vasut0e592d02018-04-13 23:13:00 +020054#define CONFIG_SPL_TEXT_BASE 0xe6300000
Marek Vasutec7113f2018-04-12 15:23:46 +020055#define CONFIG_SPL_STACK 0xe6340000
Marek Vasut0e592d02018-04-13 23:13:00 +020056#define CONFIG_SPL_MAX_SIZE 0x4000
Marek Vasutec7113f2018-04-12 15:23:46 +020057#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
Marek Vasut0e592d02018-04-13 23:13:00 +020058#ifdef CONFIG_SPL_BUILD
Marek Vasutec7113f2018-04-12 15:23:46 +020059#define CONFIG_CONS_SCIFA0
60#define CONFIG_SH_SCIF_CLK_FREQ 52000000
61#endif
Vladimir Barinov21871132015-07-20 20:49:59 +030062
63#endif /* __STOUT_H */