blob: 7cb8840dde793cada98458e17ee61d2a7e112467 [file] [log] [blame]
Kumar Gala83d40df2008-01-16 01:13:58 -06001#ifndef _FSL_LAW_H_
2#define _FSL_LAW_H_
3
4#include <asm/io.h>
5
6#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
7#define SET_LAW_ENTRY(idx, a, sz, trgt) \
8 { .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
9
10enum law_size {
11 LAW_SIZE_4K = 0xb,
12 LAW_SIZE_8K,
13 LAW_SIZE_16K,
14 LAW_SIZE_32K,
15 LAW_SIZE_64K,
16 LAW_SIZE_128K,
17 LAW_SIZE_256K,
18 LAW_SIZE_512K,
19 LAW_SIZE_1M,
20 LAW_SIZE_2M,
21 LAW_SIZE_4M,
22 LAW_SIZE_8M,
23 LAW_SIZE_16M,
24 LAW_SIZE_32M,
25 LAW_SIZE_64M,
26 LAW_SIZE_128M,
27 LAW_SIZE_256M,
28 LAW_SIZE_512M,
29 LAW_SIZE_1G,
30 LAW_SIZE_2G,
31 LAW_SIZE_4G,
32 LAW_SIZE_8G,
33 LAW_SIZE_16G,
34 LAW_SIZE_32G,
35};
36
37enum law_trgt_if {
38 LAW_TRGT_IF_PCI = 0x00,
39 LAW_TRGT_IF_PCI_2 = 0x01,
40#ifndef CONFIG_MPC8641
41 LAW_TRGT_IF_PCIE_1 = 0x02,
42#endif
43#ifndef CONFIG_MPC8572
44 LAW_TRGT_IF_PCIE_3 = 0x03,
45#endif
46 LAW_TRGT_IF_LBC = 0x04,
47 LAW_TRGT_IF_CCSR = 0x08,
48 LAW_TRGT_IF_DDR_INTRLV = 0x0b,
49 LAW_TRGT_IF_RIO = 0x0c,
50 LAW_TRGT_IF_DDR = 0x0f,
51 LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
52};
53#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR
54#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI
55#define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI
56#define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2
57
58#ifdef CONFIG_MPC8641
59#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
60#endif
61
62#ifdef CONFIG_MPC8572
63#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
64#endif
65
66struct law_entry {
67 int index;
68 phys_addr_t addr;
69 enum law_size size;
70 enum law_trgt_if trgt_id;
71};
72
73extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
74extern void disable_law(u8 idx);
75extern void init_laws(void);
76
77/* define in board code */
78extern struct law_entry law_table[];
79extern int num_law_entries;
80#endif