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York Sunee52b182012-10-11 07:13:37 +00001/*
2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
York Sunee52b182012-10-11 07:13:37 +00008 */
9
10#include <common.h>
11#include <asm/fsl_law.h>
12#include <asm/mmu.h>
13
14struct law_entry law_table[] = {
15 SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
16#ifdef CONFIG_SYS_BMAN_MEM_PHYS
17 SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
18#endif
19#ifdef CONFIG_SYS_QMAN_MEM_PHYS
20 SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
21#endif
York Sun1cb19fb2013-06-27 10:48:29 -070022#ifdef QIXIS_BASE_PHYS
York Sunee52b182012-10-11 07:13:37 +000023 SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
York Sun1cb19fb2013-06-27 10:48:29 -070024#endif
York Sunee52b182012-10-11 07:13:37 +000025#ifdef CONFIG_SYS_DCSRBAR_PHYS
Stephen George49e946c2013-03-25 07:40:12 +000026 /* Limit DCSR to 32M to access NPC Trace Buffer */
27 SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
York Sunee52b182012-10-11 07:13:37 +000028#endif
29#ifdef CONFIG_SYS_NAND_BASE_PHYS
Prabhakar Kushwahaac13eb52012-12-18 00:15:45 +000030 SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
York Sunee52b182012-10-11 07:13:37 +000031#endif
32};
33
34int num_law_entries = ARRAY_SIZE(law_table);