Michal Simek | 18a952c | 2018-03-27 10:36:39 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 2 | /* |
| 3 | * dts file for Xilinx ZynqMP zc1751-xm016-dc2 |
| 4 | * |
Michal Simek | 447fb8d | 2021-05-31 09:50:01 +0200 | [diff] [blame] | 5 | * (C) Copyright 2015 - 2021, Xilinx, Inc. |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 6 | * |
| 7 | * Michal Simek <michal.simek@xilinx.com> |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | /dts-v1/; |
| 11 | |
| 12 | #include "zynqmp.dtsi" |
Michal Simek | ee4983f | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 13 | #include "zynqmp-clk-ccf.dtsi" |
Michal Simek | bd00849 | 2021-05-10 13:14:02 +0200 | [diff] [blame] | 14 | #include <dt-bindings/gpio/gpio.h> |
| 15 | #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 16 | |
| 17 | / { |
| 18 | model = "ZynqMP zc1751-xm016-dc2 RevA"; |
| 19 | compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; |
| 20 | |
| 21 | aliases { |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 22 | ethernet0 = &gem2; |
| 23 | gpio0 = &gpio; |
| 24 | i2c0 = &i2c0; |
| 25 | rtc0 = &rtc; |
| 26 | serial0 = &uart0; |
| 27 | serial1 = &uart1; |
| 28 | spi0 = &spi0; |
| 29 | spi1 = &spi1; |
| 30 | usb0 = &usb1; |
| 31 | }; |
| 32 | |
| 33 | chosen { |
| 34 | bootargs = "earlycon"; |
| 35 | stdout-path = "serial0:115200n8"; |
| 36 | }; |
| 37 | |
Michal Simek | c926e6f | 2016-11-11 13:21:04 +0100 | [diff] [blame] | 38 | memory@0 { |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 39 | device_type = "memory"; |
| 40 | reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; |
| 41 | }; |
| 42 | }; |
| 43 | |
| 44 | &can0 { |
| 45 | status = "okay"; |
Michal Simek | bd00849 | 2021-05-10 13:14:02 +0200 | [diff] [blame] | 46 | pinctrl-names = "default"; |
| 47 | pinctrl-0 = <&pinctrl_can0_default>; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 48 | }; |
| 49 | |
| 50 | &can1 { |
| 51 | status = "okay"; |
Michal Simek | bd00849 | 2021-05-10 13:14:02 +0200 | [diff] [blame] | 52 | pinctrl-names = "default"; |
| 53 | pinctrl-0 = <&pinctrl_can1_default>; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 54 | }; |
| 55 | |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 56 | &fpd_dma_chan1 { |
| 57 | status = "okay"; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 58 | }; |
| 59 | |
| 60 | &fpd_dma_chan2 { |
| 61 | status = "okay"; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 62 | }; |
| 63 | |
| 64 | &fpd_dma_chan3 { |
| 65 | status = "okay"; |
| 66 | }; |
| 67 | |
| 68 | &fpd_dma_chan4 { |
| 69 | status = "okay"; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | &fpd_dma_chan5 { |
| 73 | status = "okay"; |
| 74 | }; |
| 75 | |
| 76 | &fpd_dma_chan6 { |
| 77 | status = "okay"; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 78 | }; |
| 79 | |
| 80 | &fpd_dma_chan7 { |
| 81 | status = "okay"; |
| 82 | }; |
| 83 | |
| 84 | &fpd_dma_chan8 { |
| 85 | status = "okay"; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 86 | }; |
| 87 | |
| 88 | &gem2 { |
| 89 | status = "okay"; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 90 | phy-handle = <&phy0>; |
| 91 | phy-mode = "rgmii-id"; |
Michal Simek | bd00849 | 2021-05-10 13:14:02 +0200 | [diff] [blame] | 92 | pinctrl-names = "default"; |
| 93 | pinctrl-0 = <&pinctrl_gem2_default>; |
Michal Simek | 2975a42 | 2019-08-08 12:44:22 +0200 | [diff] [blame] | 94 | phy0: ethernet-phy@5 { |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 95 | reg = <5>; |
| 96 | ti,rx-internal-delay = <0x8>; |
| 97 | ti,tx-internal-delay = <0xa>; |
| 98 | ti,fifo-depth = <0x1>; |
Harini Katakam | 631d9a9 | 2019-02-13 17:02:21 +0530 | [diff] [blame] | 99 | ti,dp83867-rxctrl-strap-quirk; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 100 | }; |
| 101 | }; |
| 102 | |
| 103 | &gpio { |
| 104 | status = "okay"; |
| 105 | }; |
| 106 | |
| 107 | &i2c0 { |
| 108 | status = "okay"; |
| 109 | clock-frequency = <400000>; |
Michal Simek | bd00849 | 2021-05-10 13:14:02 +0200 | [diff] [blame] | 110 | pinctrl-names = "default", "gpio"; |
| 111 | pinctrl-0 = <&pinctrl_i2c0_default>; |
| 112 | pinctrl-1 = <&pinctrl_i2c0_gpio>; |
| 113 | scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; |
| 114 | sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 115 | |
| 116 | tca6416_u26: gpio@20 { |
| 117 | compatible = "ti,tca6416"; |
| 118 | reg = <0x20>; |
| 119 | gpio-controller; |
| 120 | #gpio-cells = <2>; |
| 121 | /* IRQ not connected */ |
| 122 | }; |
| 123 | |
| 124 | rtc@68 { |
| 125 | compatible = "dallas,ds1339"; |
| 126 | reg = <0x68>; |
| 127 | }; |
| 128 | }; |
| 129 | |
| 130 | &nand0 { |
| 131 | status = "okay"; |
Michal Simek | bd00849 | 2021-05-10 13:14:02 +0200 | [diff] [blame] | 132 | pinctrl-names = "default"; |
| 133 | pinctrl-0 = <&pinctrl_nand0_default>; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 134 | arasan,has-mdma; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 135 | |
Naga Sureshkumar Relli | c3a34b8 | 2017-01-23 16:20:37 +0530 | [diff] [blame] | 136 | nand@0 { |
| 137 | reg = <0x0>; |
| 138 | #address-cells = <0x2>; |
| 139 | #size-cells = <0x1>; |
Amit Kumar Mahapatra | fbf043d | 2021-02-18 00:50:21 -0700 | [diff] [blame] | 140 | nand-ecc-mode = "soft"; |
| 141 | nand-ecc-algo = "bch"; |
| 142 | nand-rb = <0>; |
| 143 | label = "main-storage-0"; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 144 | |
Naga Sureshkumar Relli | c3a34b8 | 2017-01-23 16:20:37 +0530 | [diff] [blame] | 145 | partition@0 { /* for testing purpose */ |
| 146 | label = "nand-fsbl-uboot"; |
| 147 | reg = <0x0 0x0 0x400000>; |
| 148 | }; |
| 149 | partition@1 { /* for testing purpose */ |
| 150 | label = "nand-linux"; |
| 151 | reg = <0x0 0x400000 0x1400000>; |
| 152 | }; |
| 153 | partition@2 { /* for testing purpose */ |
| 154 | label = "nand-device-tree"; |
| 155 | reg = <0x0 0x1800000 0x400000>; |
| 156 | }; |
| 157 | partition@3 { /* for testing purpose */ |
| 158 | label = "nand-rootfs"; |
| 159 | reg = <0x0 0x1c00000 0x1400000>; |
| 160 | }; |
| 161 | partition@4 { /* for testing purpose */ |
| 162 | label = "nand-bitstream"; |
| 163 | reg = <0x0 0x3000000 0x400000>; |
| 164 | }; |
| 165 | partition@5 { /* for testing purpose */ |
| 166 | label = "nand-misc"; |
| 167 | reg = <0x0 0x3400000 0xfcc00000>; |
| 168 | }; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 169 | }; |
Naga Sureshkumar Relli | c3a34b8 | 2017-01-23 16:20:37 +0530 | [diff] [blame] | 170 | nand@1 { |
| 171 | reg = <0x1>; |
| 172 | #address-cells = <0x2>; |
| 173 | #size-cells = <0x1>; |
Amit Kumar Mahapatra | fbf043d | 2021-02-18 00:50:21 -0700 | [diff] [blame] | 174 | nand-ecc-mode = "soft"; |
| 175 | nand-ecc-algo = "bch"; |
| 176 | nand-rb = <0>; |
| 177 | label = "main-storage-1"; |
Naga Sureshkumar Relli | c3a34b8 | 2017-01-23 16:20:37 +0530 | [diff] [blame] | 178 | |
| 179 | partition@0 { /* for testing purpose */ |
| 180 | label = "nand1-fsbl-uboot"; |
| 181 | reg = <0x0 0x0 0x400000>; |
| 182 | }; |
| 183 | partition@1 { /* for testing purpose */ |
| 184 | label = "nand1-linux"; |
| 185 | reg = <0x0 0x400000 0x1400000>; |
| 186 | }; |
| 187 | partition@2 { /* for testing purpose */ |
| 188 | label = "nand1-device-tree"; |
| 189 | reg = <0x0 0x1800000 0x400000>; |
| 190 | }; |
| 191 | partition@3 { /* for testing purpose */ |
| 192 | label = "nand1-rootfs"; |
| 193 | reg = <0x0 0x1c00000 0x1400000>; |
| 194 | }; |
| 195 | partition@4 { /* for testing purpose */ |
| 196 | label = "nand1-bitstream"; |
| 197 | reg = <0x0 0x3000000 0x400000>; |
| 198 | }; |
| 199 | partition@5 { /* for testing purpose */ |
| 200 | label = "nand1-misc"; |
| 201 | reg = <0x0 0x3400000 0xfcc00000>; |
| 202 | }; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 203 | }; |
| 204 | }; |
| 205 | |
Michal Simek | bd00849 | 2021-05-10 13:14:02 +0200 | [diff] [blame] | 206 | &pinctrl0 { |
| 207 | status = "okay"; |
| 208 | pinctrl_can0_default: can0-default { |
| 209 | mux { |
| 210 | function = "can0"; |
| 211 | groups = "can0_9_grp"; |
| 212 | }; |
| 213 | |
| 214 | conf { |
| 215 | groups = "can0_9_grp"; |
| 216 | slew-rate = <SLEW_RATE_SLOW>; |
| 217 | power-source = <IO_STANDARD_LVCMOS18>; |
| 218 | }; |
| 219 | |
| 220 | conf-rx { |
| 221 | pins = "MIO38"; |
| 222 | bias-high-impedance; |
| 223 | }; |
| 224 | |
| 225 | conf-tx { |
| 226 | pins = "MIO39"; |
| 227 | bias-disable; |
| 228 | }; |
| 229 | }; |
| 230 | |
| 231 | pinctrl_can1_default: can1-default { |
| 232 | mux { |
| 233 | function = "can1"; |
| 234 | groups = "can1_8_grp"; |
| 235 | }; |
| 236 | |
| 237 | conf { |
| 238 | groups = "can1_8_grp"; |
| 239 | slew-rate = <SLEW_RATE_SLOW>; |
| 240 | power-source = <IO_STANDARD_LVCMOS18>; |
| 241 | }; |
| 242 | |
| 243 | conf-rx { |
| 244 | pins = "MIO33"; |
| 245 | bias-high-impedance; |
| 246 | }; |
| 247 | |
| 248 | conf-tx { |
| 249 | pins = "MIO32"; |
| 250 | bias-disable; |
| 251 | }; |
| 252 | }; |
| 253 | |
| 254 | pinctrl_i2c0_default: i2c0-default { |
| 255 | mux { |
| 256 | groups = "i2c0_1_grp"; |
| 257 | function = "i2c0"; |
| 258 | }; |
| 259 | |
| 260 | conf { |
| 261 | groups = "i2c0_1_grp"; |
| 262 | bias-pull-up; |
| 263 | slew-rate = <SLEW_RATE_SLOW>; |
| 264 | power-source = <IO_STANDARD_LVCMOS18>; |
| 265 | }; |
| 266 | }; |
| 267 | |
| 268 | pinctrl_i2c0_gpio: i2c0-gpio { |
| 269 | mux { |
| 270 | groups = "gpio0_6_grp", "gpio0_7_grp"; |
| 271 | function = "gpio0"; |
| 272 | }; |
| 273 | |
| 274 | conf { |
| 275 | groups = "gpio0_6_grp", "gpio0_7_grp"; |
| 276 | slew-rate = <SLEW_RATE_SLOW>; |
| 277 | power-source = <IO_STANDARD_LVCMOS18>; |
| 278 | }; |
| 279 | }; |
| 280 | |
| 281 | pinctrl_uart0_default: uart0-default { |
| 282 | mux { |
| 283 | groups = "uart0_10_grp"; |
| 284 | function = "uart0"; |
| 285 | }; |
| 286 | |
| 287 | conf { |
| 288 | groups = "uart0_10_grp"; |
| 289 | slew-rate = <SLEW_RATE_SLOW>; |
| 290 | power-source = <IO_STANDARD_LVCMOS18>; |
| 291 | }; |
| 292 | |
| 293 | conf-rx { |
| 294 | pins = "MIO42"; |
| 295 | bias-high-impedance; |
| 296 | }; |
| 297 | |
| 298 | conf-tx { |
| 299 | pins = "MIO43"; |
| 300 | bias-disable; |
| 301 | }; |
| 302 | }; |
| 303 | |
| 304 | pinctrl_uart1_default: uart1-default { |
| 305 | mux { |
| 306 | groups = "uart1_10_grp"; |
| 307 | function = "uart1"; |
| 308 | }; |
| 309 | |
| 310 | conf { |
| 311 | groups = "uart1_10_grp"; |
| 312 | slew-rate = <SLEW_RATE_SLOW>; |
| 313 | power-source = <IO_STANDARD_LVCMOS18>; |
| 314 | }; |
| 315 | |
| 316 | conf-rx { |
| 317 | pins = "MIO41"; |
| 318 | bias-high-impedance; |
| 319 | }; |
| 320 | |
| 321 | conf-tx { |
| 322 | pins = "MIO40"; |
| 323 | bias-disable; |
| 324 | }; |
| 325 | }; |
| 326 | |
| 327 | pinctrl_usb1_default: usb1-default { |
| 328 | mux { |
| 329 | groups = "usb1_0_grp"; |
| 330 | function = "usb1"; |
| 331 | }; |
| 332 | |
| 333 | conf { |
| 334 | groups = "usb1_0_grp"; |
| 335 | slew-rate = <SLEW_RATE_SLOW>; |
| 336 | power-source = <IO_STANDARD_LVCMOS18>; |
| 337 | }; |
| 338 | |
| 339 | conf-rx { |
| 340 | pins = "MIO64", "MIO65", "MIO67"; |
| 341 | bias-high-impedance; |
| 342 | }; |
| 343 | |
| 344 | conf-tx { |
| 345 | pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", |
| 346 | "MIO72", "MIO73", "MIO74", "MIO75"; |
| 347 | bias-disable; |
| 348 | }; |
| 349 | }; |
| 350 | |
| 351 | pinctrl_gem2_default: gem2-default { |
| 352 | mux { |
| 353 | function = "ethernet2"; |
| 354 | groups = "ethernet2_0_grp"; |
| 355 | }; |
| 356 | |
| 357 | conf { |
| 358 | groups = "ethernet2_0_grp"; |
| 359 | slew-rate = <SLEW_RATE_SLOW>; |
| 360 | power-source = <IO_STANDARD_LVCMOS18>; |
| 361 | }; |
| 362 | |
| 363 | conf-rx { |
| 364 | pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", |
| 365 | "MIO63"; |
| 366 | bias-high-impedance; |
| 367 | low-power-disable; |
| 368 | }; |
| 369 | |
| 370 | conf-tx { |
| 371 | pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", |
| 372 | "MIO57"; |
| 373 | bias-disable; |
| 374 | low-power-enable; |
| 375 | }; |
| 376 | |
| 377 | mux-mdio { |
| 378 | function = "mdio2"; |
| 379 | groups = "mdio2_0_grp"; |
| 380 | }; |
| 381 | |
| 382 | conf-mdio { |
| 383 | groups = "mdio2_0_grp"; |
| 384 | slew-rate = <SLEW_RATE_SLOW>; |
| 385 | power-source = <IO_STANDARD_LVCMOS18>; |
| 386 | bias-disable; |
| 387 | }; |
| 388 | }; |
| 389 | |
| 390 | pinctrl_nand0_default: nand0-default { |
| 391 | mux { |
| 392 | groups = "nand0_0_grp"; |
| 393 | function = "nand0"; |
| 394 | }; |
| 395 | |
| 396 | conf { |
| 397 | groups = "nand0_0_grp"; |
| 398 | bias-pull-up; |
| 399 | }; |
| 400 | |
| 401 | mux-ce { |
| 402 | groups = "nand0_ce_0_grp"; |
| 403 | function = "nand0_ce"; |
| 404 | }; |
| 405 | |
| 406 | conf-ce { |
| 407 | groups = "nand0_ce_0_grp"; |
| 408 | bias-pull-up; |
| 409 | }; |
| 410 | |
| 411 | mux-rb { |
| 412 | groups = "nand0_rb_0_grp"; |
| 413 | function = "nand0_rb"; |
| 414 | }; |
| 415 | |
| 416 | conf-rb { |
| 417 | groups = "nand0_rb_0_grp"; |
| 418 | bias-pull-up; |
| 419 | }; |
| 420 | |
| 421 | mux-dqs { |
| 422 | groups = "nand0_dqs_0_grp"; |
| 423 | function = "nand0_dqs"; |
| 424 | }; |
| 425 | |
| 426 | conf-dqs { |
| 427 | groups = "nand0_dqs_0_grp"; |
| 428 | bias-pull-up; |
| 429 | }; |
| 430 | }; |
| 431 | |
| 432 | pinctrl_spi0_default: spi0-default { |
| 433 | mux { |
| 434 | groups = "spi0_0_grp"; |
| 435 | function = "spi0"; |
| 436 | }; |
| 437 | |
| 438 | conf { |
| 439 | groups = "spi0_0_grp"; |
| 440 | bias-disable; |
| 441 | slew-rate = <SLEW_RATE_SLOW>; |
| 442 | power-source = <IO_STANDARD_LVCMOS18>; |
| 443 | }; |
| 444 | |
| 445 | mux-cs { |
| 446 | groups = "spi0_ss_0_grp", "spi0_ss_1_grp", |
| 447 | "spi0_ss_2_grp"; |
| 448 | function = "spi0_ss"; |
| 449 | }; |
| 450 | |
| 451 | conf-cs { |
| 452 | groups = "spi0_ss_0_grp", "spi0_ss_1_grp", |
| 453 | "spi0_ss_2_grp"; |
| 454 | bias-disable; |
| 455 | }; |
| 456 | }; |
| 457 | |
| 458 | pinctrl_spi1_default: spi1-default { |
| 459 | mux { |
| 460 | groups = "spi1_3_grp"; |
| 461 | function = "spi1"; |
| 462 | }; |
| 463 | |
| 464 | conf { |
| 465 | groups = "spi1_3_grp"; |
| 466 | bias-disable; |
| 467 | slew-rate = <SLEW_RATE_SLOW>; |
| 468 | power-source = <IO_STANDARD_LVCMOS18>; |
| 469 | }; |
| 470 | |
| 471 | mux-cs { |
| 472 | groups = "spi1_ss_9_grp", "spi1_ss_10_grp", |
| 473 | "spi1_ss_11_grp"; |
| 474 | function = "spi1_ss"; |
| 475 | }; |
| 476 | |
| 477 | conf-cs { |
| 478 | groups = "spi1_ss_9_grp", "spi1_ss_10_grp", |
| 479 | "spi1_ss_11_grp"; |
| 480 | bias-disable; |
| 481 | }; |
| 482 | }; |
| 483 | }; |
| 484 | |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 485 | &rtc { |
| 486 | status = "okay"; |
| 487 | }; |
| 488 | |
| 489 | &spi0 { |
| 490 | status = "okay"; |
| 491 | num-cs = <1>; |
Michal Simek | bd00849 | 2021-05-10 13:14:02 +0200 | [diff] [blame] | 492 | pinctrl-names = "default"; |
| 493 | pinctrl-0 = <&pinctrl_spi0_default>; |
| 494 | |
Michal Simek | ba9da60 | 2018-03-27 13:09:15 +0200 | [diff] [blame] | 495 | spi0_flash0: flash@0 { |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 496 | #address-cells = <1>; |
| 497 | #size-cells = <1>; |
Michal Simek | ba9da60 | 2018-03-27 13:09:15 +0200 | [diff] [blame] | 498 | compatible = "sst,sst25wf080", "jedec,spi-nor"; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 499 | spi-max-frequency = <50000000>; |
| 500 | reg = <0>; |
| 501 | |
Michal Simek | ba9da60 | 2018-03-27 13:09:15 +0200 | [diff] [blame] | 502 | partition@0 { |
Amit Kumar Mahapatra | 0546b1a | 2020-02-17 07:50:05 -0700 | [diff] [blame] | 503 | label = "spi0-data"; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 504 | reg = <0x0 0x100000>; |
| 505 | }; |
| 506 | }; |
| 507 | }; |
| 508 | |
| 509 | &spi1 { |
| 510 | status = "okay"; |
| 511 | num-cs = <1>; |
Michal Simek | bd00849 | 2021-05-10 13:14:02 +0200 | [diff] [blame] | 512 | pinctrl-names = "default"; |
| 513 | pinctrl-0 = <&pinctrl_spi1_default>; |
| 514 | |
Michal Simek | ba9da60 | 2018-03-27 13:09:15 +0200 | [diff] [blame] | 515 | spi1_flash0: flash@0 { |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 516 | #address-cells = <1>; |
| 517 | #size-cells = <1>; |
Michal Simek | ba9da60 | 2018-03-27 13:09:15 +0200 | [diff] [blame] | 518 | compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 519 | spi-max-frequency = <20000000>; |
| 520 | reg = <0>; |
| 521 | |
Michal Simek | ba9da60 | 2018-03-27 13:09:15 +0200 | [diff] [blame] | 522 | partition@0 { |
Amit Kumar Mahapatra | 0546b1a | 2020-02-17 07:50:05 -0700 | [diff] [blame] | 523 | label = "spi1-data"; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 524 | reg = <0x0 0x84000>; |
| 525 | }; |
| 526 | }; |
| 527 | }; |
| 528 | |
| 529 | /* ULPI SMSC USB3320 */ |
| 530 | &usb1 { |
| 531 | status = "okay"; |
Michal Simek | bd00849 | 2021-05-10 13:14:02 +0200 | [diff] [blame] | 532 | pinctrl-names = "default"; |
| 533 | pinctrl-0 = <&pinctrl_usb1_default>; |
Michal Simek | 8925e59 | 2016-04-05 12:01:16 +0200 | [diff] [blame] | 534 | }; |
| 535 | |
| 536 | &dwc3_1 { |
| 537 | status = "okay"; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 538 | dr_mode = "host"; |
Michal Simek | 83dc133 | 2021-06-11 08:52:25 +0200 | [diff] [blame^] | 539 | snps,usb3_lpm_capable; |
| 540 | maximum-speed = "super-speed"; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 541 | }; |
| 542 | |
| 543 | &uart0 { |
| 544 | status = "okay"; |
Michal Simek | bd00849 | 2021-05-10 13:14:02 +0200 | [diff] [blame] | 545 | pinctrl-names = "default"; |
| 546 | pinctrl-0 = <&pinctrl_uart0_default>; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 547 | }; |
| 548 | |
| 549 | &uart1 { |
| 550 | status = "okay"; |
Michal Simek | bd00849 | 2021-05-10 13:14:02 +0200 | [diff] [blame] | 551 | pinctrl-names = "default"; |
| 552 | pinctrl-0 = <&pinctrl_uart1_default>; |
Michal Simek | 6c0c958 | 2016-04-07 16:00:11 +0200 | [diff] [blame] | 553 | }; |