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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamadad5cf3292016-03-18 16:41:52 +09002/*
3 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadad5cf3292016-03-18 16:41:52 +09004 */
5
Masahiro Yamadad5cf3292016-03-18 16:41:52 +09006#include <debug_uart.h>
7#include <linux/io.h>
8#include <linux/serial_reg.h>
9
Masahiro Yamada69492fb2019-06-29 02:38:06 +090010#include "../sg-regs.h"
Masahiro Yamadad5cf3292016-03-18 16:41:52 +090011#include "../soc-info.h"
12#include "debug-uart.h"
13
14#define UNIPHIER_UART_TX 0x00
15#define UNIPHIER_UART_LCR_MCR 0x10
16#define UNIPHIER_UART_LSR 0x14
17#define UNIPHIER_UART_LDR 0x24
18
19static void _debug_uart_putc(int c)
20{
21 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
22
23 while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE))
24 ;
25
26 writel(c, base + UNIPHIER_UART_TX);
27}
28
Masahiro Yamada69492fb2019-06-29 02:38:06 +090029#ifdef CONFIG_SPL_BUILD
30void sg_set_pinsel(unsigned int pin, unsigned int muxval,
31 unsigned int mux_bits, unsigned int reg_stride)
32{
33 unsigned int shift = pin * mux_bits % 32;
Masahiro Yamadad41b3582019-07-10 20:07:40 +090034 void __iomem *reg = sg_base + SG_PINCTRL_BASE +
35 pin * mux_bits / 32 * reg_stride;
Masahiro Yamada69492fb2019-06-29 02:38:06 +090036 u32 mask = (1U << mux_bits) - 1;
37 u32 tmp;
38
39 tmp = readl(reg);
40 tmp &= ~(mask << shift);
41 tmp |= (mask & muxval) << shift;
42 writel(tmp, reg);
43}
44
45void sg_set_iectrl(unsigned int pin)
46{
47 unsigned int bit = pin % 32;
Masahiro Yamadad41b3582019-07-10 20:07:40 +090048 void __iomem *reg = sg_base + SG_IECTRL + pin / 32 * 4;
Masahiro Yamada69492fb2019-06-29 02:38:06 +090049 u32 tmp;
50
51 tmp = readl(reg);
52 tmp |= 1 << bit;
53 writel(tmp, reg);
54}
55#endif
56
Masahiro Yamadad5cf3292016-03-18 16:41:52 +090057void _debug_uart_init(void)
58{
Masahiro Yamadae3d5d3a2019-06-29 02:38:05 +090059#ifdef CONFIG_SPL_BUILD
Masahiro Yamadad5cf3292016-03-18 16:41:52 +090060 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
61 unsigned int divisor;
62
Masahiro Yamadae27d6c72017-01-21 18:05:26 +090063 switch (uniphier_get_soc_id()) {
Masahiro Yamadad5cf3292016-03-18 16:41:52 +090064#if defined(CONFIG_ARCH_UNIPHIER_LD4)
Masahiro Yamadae27d6c72017-01-21 18:05:26 +090065 case UNIPHIER_LD4_ID:
Masahiro Yamadad5cf3292016-03-18 16:41:52 +090066 divisor = uniphier_ld4_debug_uart_init();
67 break;
68#endif
69#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
Masahiro Yamadae27d6c72017-01-21 18:05:26 +090070 case UNIPHIER_PRO4_ID:
Masahiro Yamadad5cf3292016-03-18 16:41:52 +090071 divisor = uniphier_pro4_debug_uart_init();
72 break;
73#endif
74#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
Masahiro Yamadae27d6c72017-01-21 18:05:26 +090075 case UNIPHIER_SLD8_ID:
Masahiro Yamadad5cf3292016-03-18 16:41:52 +090076 divisor = uniphier_sld8_debug_uart_init();
77 break;
78#endif
79#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
Masahiro Yamadae27d6c72017-01-21 18:05:26 +090080 case UNIPHIER_PRO5_ID:
Masahiro Yamadad5cf3292016-03-18 16:41:52 +090081 divisor = uniphier_pro5_debug_uart_init();
82 break;
83#endif
84#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
Masahiro Yamadae27d6c72017-01-21 18:05:26 +090085 case UNIPHIER_PXS2_ID:
Masahiro Yamadad5cf3292016-03-18 16:41:52 +090086 divisor = uniphier_pxs2_debug_uart_init();
87 break;
88#endif
89#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
Masahiro Yamadae27d6c72017-01-21 18:05:26 +090090 case UNIPHIER_LD6B_ID:
Masahiro Yamadad5cf3292016-03-18 16:41:52 +090091 divisor = uniphier_ld6b_debug_uart_init();
92 break;
93#endif
Masahiro Yamadad5cf3292016-03-18 16:41:52 +090094 default:
95 return;
96 }
97
98 writel(UART_LCR_WLEN8 << 8, base + UNIPHIER_UART_LCR_MCR);
99
100 writel(divisor, base + UNIPHIER_UART_LDR);
Masahiro Yamadae3d5d3a2019-06-29 02:38:05 +0900101#endif
Masahiro Yamadad5cf3292016-03-18 16:41:52 +0900102}
103DEBUG_UART_FUNCS