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wdenkc6097192002-11-03 00:24:07 +00001/*
wdenkc837dcb2004-01-20 23:12:12 +00002 * (C) Copyright 2000-2004
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * David Updegraff, Cray, Inc. dave@cray.com: our 405 is walnut-lite..
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#define CONFIG_CRAYL1
32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
36
37#define CONFIG_405GP 1 /* This is a PPC405 CPU */
38#define CONFIG_4xx 1 /* ...member of PPC405 family */
39#define CONFIG_SYS_CLK_FREQ 25000000
40#define CONFIG_BAUDRATE 9600
41#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
42#define CONFIG_MII 1 /* MII PHY management */
43#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */
wdenkc837dcb2004-01-20 23:12:12 +000044#define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */
wdenkc6097192002-11-03 00:24:07 +000045#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */
46
47/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
48 * keep possible initrd ramdisk decompression out. This is in k (1024 bytes)
wdenk8bde7f72003-06-27 21:31:46 +000049 #define CONFIG_PRAM 16
wdenkc6097192002-11-03 00:24:07 +000050 */
wdenk7f70e852003-05-20 14:25:27 +000051#define CONFIG_LOADADDR 0x100000 /* where TFTP images go */
wdenkc6097192002-11-03 00:24:07 +000052#undef CONFIG_BOOTARGS
53
wdenk7f70e852003-05-20 14:25:27 +000054/* Bootcmd is overridden by the bootscript in board/cray/L1
wdenkc6097192002-11-03 00:24:07 +000055 */
wdenk7f70e852003-05-20 14:25:27 +000056#define CFG_AUTOLOAD "no"
57#define CONFIG_BOOTCOMMAND "dhcp"
wdenkc6097192002-11-03 00:24:07 +000058
wdenk8bde7f72003-06-27 21:31:46 +000059/*
wdenkc6097192002-11-03 00:24:07 +000060 * ..during experiments..
61 #define CONFIG_SERVERIP 10.0.0.1
wdenk8bde7f72003-06-27 21:31:46 +000062 #define CONFIG_ETHADDR 00:40:a6:80:14:5
wdenkc6097192002-11-03 00:24:07 +000063 */
64#define CONFIG_HARD_I2C 1 /* hardware support for i2c */
wdenk7f70e852003-05-20 14:25:27 +000065#define CONFIG_SDRAM_BANK0 1
wdenkc6097192002-11-03 00:24:07 +000066#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
67#define CFG_I2C_SLAVE 0x7F
68#define CFG_I2C_EEPROM_ADDR 0x57
69#define CFG_I2C_EEPROM_ADDR_LEN 1
70#define CONFIG_IDENT_STRING "Cray L1"
71#define CONFIG_ENV_OVERWRITE 1
72#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
73#define CFG_HUSH_PARSER 1
74#define CFG_PROMPT_HUSH_PS2 "> "
wdenk7f70e852003-05-20 14:25:27 +000075#define CONFIG_AUTOSCRIPT 1
wdenkc6097192002-11-03 00:24:07 +000076
77
Jon Loeliger49cf7e82007-07-05 19:52:35 -050078/*
79 * Command line configuration.
80 */
81
82#define CONFIG_CMD_BDI
83#define CONFIG_CMD_IMI
84#define CONFIG_CMD_FLASH
85#define CONFIG_CMD_MEMORY
86#define CONFIG_CMD_NET
87#define CONFIG_CMD_ENV
88#define CONFIG_CMD_CONSOLE
89#define CONFIG_CMD_ASKENV
90#define CONFIG_CMD_ECHO
91#define CONFIG_CMD_IMMAP
92#define CONFIG_CMD_REGINFO
93#define CONFIG_CMD_DHCP
94#define CONFIG_CMD_DATE
95#define CONFIG_CMD_RUN
96#define CONFIG_CMD_I2C
97#define CONFIG_CMD_EEPROM
98#define CONFIG_CMD_DIAG
99#define CONFIG_CMD_AUTOSCRIPT
100#define CONFIG_CMD_SETGETDCR
101
wdenkc6097192002-11-03 00:24:07 +0000102
103/*
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500104 * BOOTP options
wdenkc6097192002-11-03 00:24:07 +0000105 */
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500106#define CONFIG_BOOTP_SUBNETMASK
107#define CONFIG_BOOTP_GATEWAY
108#define CONFIG_BOOTP_HOSTNAME
109#define CONFIG_BOOTP_BOOTPATH
110#define CONFIG_BOOTP_VENDOREX
111#define CONFIG_BOOTP_DNS
112#define CONFIG_BOOTP_BOOTFILESIZE
113
wdenkc6097192002-11-03 00:24:07 +0000114
wdenk8bde7f72003-06-27 21:31:46 +0000115/*
wdenk7f70e852003-05-20 14:25:27 +0000116 * how many time to fail & restart a net-TFTP before giving up & resetting
117 * the board hoping that a reset of net interface might help..
118 */
119#define CONFIG_NET_RESET 5
120
wdenk8bde7f72003-06-27 21:31:46 +0000121/*
wdenkc6097192002-11-03 00:24:07 +0000122 * bauds. Just to make it compile; in our case, I read the base_baud
123 * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
124 * drives the system clock.
125 */
126#define CFG_BASE_BAUD 403225
127#define CFG_BAUDRATE_TABLE \
128 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
129
wdenkc6097192002-11-03 00:24:07 +0000130/*
131 * Miscellaneous configurable options
132 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200133#define CFG_PROMPT "=> " /* Monitor Command Prompt */
wdenkc6097192002-11-03 00:24:07 +0000134#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200135#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
136#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000137#define CFG_MAXARGS 16 /* max number of command args */
138
139
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200140#define CFG_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */
wdenkc6097192002-11-03 00:24:07 +0000141#define CFG_TFTP_LOADADDR CFG_LOAD_ADDR
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200142#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenk7f70e852003-05-20 14:25:27 +0000143#define CFG_DRAM_TEST 1
wdenkc6097192002-11-03 00:24:07 +0000144
145/*-----------------------------------------------------------------------
146 * Start addresses for the final memory configuration
147 * (Set up by the startup code)
148 * Please note that CFG_SDRAM_BASE _must_ start at 0
149 */
150#define CFG_SDRAM_BASE 0x00000000
151#define CFG_FLASH_BASE 0xFFC00000
152#define CFG_MONITOR_BASE TEXT_BASE
153
wdenkc6097192002-11-03 00:24:07 +0000154
wdenk7f70e852003-05-20 14:25:27 +0000155#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
wdenkc6097192002-11-03 00:24:07 +0000156
157/*
158 * For booting Linux, the board info and command line data
159 * have to be in the first 8 MB of memory, since this is
160 * the maximum mapped by the Linux kernel during initialization.
161 */
162#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
163/*-----------------------------------------------------------------------
164 * FLASH organization
165 */
166#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
167#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
168#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
169#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
170
171/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */
wdenk8bde7f72003-06-27 21:31:46 +0000172#define CFG_ENV_OFFSET 0x3c8000
wdenkc6097192002-11-03 00:24:07 +0000173#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
wdenk7f70e852003-05-20 14:25:27 +0000174#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment area */
wdenkc6097192002-11-03 00:24:07 +0000175#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
176
wdenk7f70e852003-05-20 14:25:27 +0000177/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
wdenkc6097192002-11-03 00:24:07 +0000178 * 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
179 */
180#define CFG_SDRAM_SIZE 32 /* megs of ram */
181#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
182 /* the exception vector table */
183 /* to the end of the DRAM */
184 /* less monitor and malloc area */
185#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
wdenk7f70e852003-05-20 14:25:27 +0000186#define CFG_MALLOC_LEN (128 << 10) /* 128k for malloc space */
wdenkc6097192002-11-03 00:24:07 +0000187#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
wdenk8bde7f72003-06-27 21:31:46 +0000188 + CFG_MALLOC_LEN \
189 + CFG_ENV_SECT_SIZE \
190 + CFG_STACK_USAGE )
wdenkc6097192002-11-03 00:24:07 +0000191
192#define CFG_MEMTEST_END (CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE)
193/* END ENVIRONNEMENT FLASH */
194
wdenkc6097192002-11-03 00:24:07 +0000195/*
196 * Init Memory Controller:
197 *
198 * BR0/1 and OR0/1 (FLASH)
199 */
200
201#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
202
203
204/*-----------------------------------------------------------------------
205 * Definitions for initial stack pointer and data area (in OnChipMem )
206 */
wdenk7f70e852003-05-20 14:25:27 +0000207#if 1
208/* On Chip Memory location */
wdenkc6097192002-11-03 00:24:07 +0000209#define CFG_TEMP_STACK_OCM 1
210#define CFG_OCM_DATA_ADDR 0xF0000000
211#define CFG_OCM_DATA_SIZE 0x1000
wdenk7f70e852003-05-20 14:25:27 +0000212
213#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
214#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
215#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
216#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
217#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
218#else
219#define CFG_OCM_DATA_ADDR 0xF0000000
220#define CFG_OCM_DATA_SIZE 0x1000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200221#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
wdenkc6097192002-11-03 00:24:07 +0000222#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
wdenkc6097192002-11-03 00:24:07 +0000223#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
224#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
225#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenk7f70e852003-05-20 14:25:27 +0000226#endif
wdenkc6097192002-11-03 00:24:07 +0000227
228/*-----------------------------------------------------------------------
229 * Definitions for Serial Presence Detect EEPROM address
230 */
231#define EEPROM_WRITE_ADDRESS 0xA0
232#define EEPROM_READ_ADDRESS 0xA1
233
234/*
235 * Internal Definitions
236 *
237 * Boot Flags
238 */
239#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
240#define BOOTFLAG_WARM 0x02 /* Software reboot */
241
242#endif /* __CONFIG_H */