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wdenkc6097192002-11-03 00:24:07 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 *
26 * Configuration settings for the CU824 board.
27 *
28 */
29
30/* ------------------------------------------------------------------------- */
31
32/*
33 * board/config.h - configuration options, board specific
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
44#define CONFIG_MPC824X 1
45#define CONFIG_MPC8240 1
46#define CONFIG_CU824 1
47
48
49#define CONFIG_CONS_INDEX 1
50#define CONFIG_BAUDRATE 9600
51#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
52
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010053#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkc6097192002-11-03 00:24:07 +000054
55#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
56#define CONFIG_BOOTDELAY 5
57
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050058/*
59 * BOOTP options
60 */
61#define CONFIG_BOOTP_SUBNETMASK
62#define CONFIG_BOOTP_GATEWAY
63#define CONFIG_BOOTP_HOSTNAME
64#define CONFIG_BOOTP_BOOTPATH
65#define CONFIG_BOOTP_BOOTFILESIZE
66
wdenkc6097192002-11-03 00:24:07 +000067
wdenk414eec32005-04-02 22:37:54 +000068#define CONFIG_TIMESTAMP /* Print image info with timestamp */
69
wdenkc6097192002-11-03 00:24:07 +000070
Jon Loeliger49cf7e82007-07-05 19:52:35 -050071/*
72 * Command line configuration.
wdenkc6097192002-11-03 00:24:07 +000073 */
Jon Loeliger49cf7e82007-07-05 19:52:35 -050074#include <config_cmd_default.h>
75
Wolfgang Denk5728be32007-08-06 01:01:49 +020076#define CONFIG_CMD_BEDBUG
Jon Loeliger49cf7e82007-07-05 19:52:35 -050077#define CONFIG_CMD_DHCP
78#define CONFIG_CMD_PCI
79#define CONFIG_CMD_NFS
80#define CONFIG_CMD_SNTP
wdenkc6097192002-11-03 00:24:07 +000081
82
83/*
84 * Miscellaneous configurable options
85 */
86#define CFG_LONGHELP /* undef to save memory */
87#define CFG_PROMPT "=> " /* Monitor Command Prompt */
88#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
89
90#if 1
91#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
92#endif
93#ifdef CFG_HUSH_PARSER
94#define CFG_PROMPT_HUSH_PS2 "> "
95#endif
96
97/* Print Buffer Size
98 */
99#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
100
101#define CFG_MAXARGS 16 /* max number of command args */
102#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
103#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
104
105/*-----------------------------------------------------------------------
106 * Start addresses for the final memory configuration
107 * (Set up by the startup code)
108 * Please note that CFG_SDRAM_BASE _must_ start at 0
109 */
110#define CFG_SDRAM_BASE 0x00000000
111#define CFG_FLASH_BASE 0xFF000000
112
113#define CFG_RESET_ADDRESS 0xFFF00100
114
115#define CFG_EUMB_ADDR 0xFCE00000
116
117#define CFG_MONITOR_BASE TEXT_BASE
118
119#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
120#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
121
122#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
123#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
124
125 /* Maximum amount of RAM.
126 */
127#define CFG_MAX_RAM_SIZE 0x10000000
128
129
130#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
131#undef CFG_RAMBOOT
132#else
133#define CFG_RAMBOOT
134#endif
135
136
137/*-----------------------------------------------------------------------
138 * Definitions for initial stack pointer and data area
139 */
140
141 /* Size in bytes reserved for initial data
142 */
143#define CFG_GBL_DATA_SIZE 128
144
145#define CFG_INIT_RAM_ADDR 0x40000000
146#define CFG_INIT_RAM_END 0x1000
147#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
148
149/*
150 * NS16550 Configuration
151 */
152#define CFG_NS16550
153#define CFG_NS16550_SERIAL
154
155#define CFG_NS16550_REG_SIZE 4
156
157#define CFG_NS16550_CLK (14745600 / 2)
158
159#define CFG_NS16550_COM1 0xFE800080
160#define CFG_NS16550_COM2 0xFE8000C0
161
162/*
163 * Low Level Configuration Settings
164 * (address mappings, register initial values, etc.)
165 * You should know what you are doing if you make changes here.
166 * For the detail description refer to the MPC8240 user's manual.
167 */
168
169#define CONFIG_SYS_CLK_FREQ 33000000
170#define CFG_HZ 1000
171
172 /* Bit-field values for MCCR1.
173 */
174#define CFG_ROMNAL 0
175#define CFG_ROMFAL 7
176
177 /* Bit-field values for MCCR2.
178 */
179#define CFG_REFINT 430 /* Refresh interval */
180
181 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
182 */
183#define CFG_BSTOPRE 192
184
185 /* Bit-field values for MCCR3.
186 */
187#define CFG_REFREC 2 /* Refresh to activate interval */
188#define CFG_RDLAT 3 /* Data latancy from read command */
189
190 /* Bit-field values for MCCR4.
191 */
192#define CFG_PRETOACT 2 /* Precharge to activate interval */
193#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
194#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
195#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
196#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
197#define CFG_ACTORW 2
198#define CFG_REGISTERD_TYPE_BUFFER 1
199
200/* Memory bank settings.
201 * Only bits 20-29 are actually used from these vales to set the
202 * start/end addresses. The upper two bits will always be 0, and the lower
203 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
204 * address. Refer to the MPC8240 book.
205 */
206
207#define CFG_BANK0_START 0x00000000
208#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
209#define CFG_BANK0_ENABLE 1
210#define CFG_BANK1_START 0x3ff00000
211#define CFG_BANK1_END 0x3fffffff
212#define CFG_BANK1_ENABLE 0
213#define CFG_BANK2_START 0x3ff00000
214#define CFG_BANK2_END 0x3fffffff
215#define CFG_BANK2_ENABLE 0
216#define CFG_BANK3_START 0x3ff00000
217#define CFG_BANK3_END 0x3fffffff
218#define CFG_BANK3_ENABLE 0
219#define CFG_BANK4_START 0x3ff00000
220#define CFG_BANK4_END 0x3fffffff
221#define CFG_BANK4_ENABLE 0
222#define CFG_BANK5_START 0x3ff00000
223#define CFG_BANK5_END 0x3fffffff
224#define CFG_BANK5_ENABLE 0
225#define CFG_BANK6_START 0x3ff00000
226#define CFG_BANK6_END 0x3fffffff
227#define CFG_BANK6_ENABLE 0
228#define CFG_BANK7_START 0x3ff00000
229#define CFG_BANK7_END 0x3fffffff
230#define CFG_BANK7_ENABLE 0
231
232#define CFG_ODCR 0xff
233
234#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
235#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
236
237#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
238#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
239
240#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
241#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
242
243#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
244#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
245
246#define CFG_DBAT0L CFG_IBAT0L
247#define CFG_DBAT0U CFG_IBAT0U
248#define CFG_DBAT1L CFG_IBAT1L
249#define CFG_DBAT1U CFG_IBAT1U
250#define CFG_DBAT2L CFG_IBAT2L
251#define CFG_DBAT2U CFG_IBAT2U
252#define CFG_DBAT3L CFG_IBAT3L
253#define CFG_DBAT3U CFG_IBAT3U
254
255/*
256 * For booting Linux, the board info and command line data
257 * have to be in the first 8 MB of memory, since this is
258 * the maximum mapped by the Linux kernel during initialization.
259 */
260#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
261
262/*-----------------------------------------------------------------------
263 * FLASH organization
264 */
265#define CFG_MAX_FLASH_BANKS 2 /* Max number of flash banks */
266#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
267
268#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
269#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
270
271 /* Warining: environment is not EMBEDDED in the U-Boot code.
272 * It's stored in flash separately.
273 */
274#define CFG_ENV_IS_IN_FLASH 1
275#if 0
276#define CFG_ENV_ADDR 0xFF008000
277#define CFG_ENV_SIZE 0x8000 /* Size of the Environment Sector */
278#else
279#define CFG_ENV_ADDR 0xFFFC0000
280#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */
281#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
282#define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
283#endif
284
285/*-----------------------------------------------------------------------
286 * Cache Configuration
287 */
288#define CFG_CACHELINE_SIZE 32
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500289#if defined(CONFIG_CMD_KGDB)
wdenkc6097192002-11-03 00:24:07 +0000290# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
291#endif
292
293/*
294 * Internal Definitions
295 *
296 * Boot Flags
297 */
298#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
299#define BOOTFLAG_WARM 0x02 /* Software reboot */
300
301/*-----------------------------------------------------------------------
302 * PCI stuff
303 *-----------------------------------------------------------------------
304 */
305#define CONFIG_PCI /* include pci support */
306#undef CONFIG_PCI_PNP
307
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200308#define CONFIG_NET_MULTI /* Multi ethernet cards support */
wdenkc6097192002-11-03 00:24:07 +0000309
310#define CONFIG_TULIP
311#define CONFIG_TULIP_USE_IO
312
313#define CFG_ETH_DEV_FN 0x7800
314#define CFG_ETH_IOBASE 0x00104000
315
wdenk3bac3512003-03-12 10:41:04 +0000316#define CONFIG_EEPRO100
stroese53cf9432003-06-05 15:39:44 +0000317#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk3bac3512003-03-12 10:41:04 +0000318#define PCI_ENET0_IOADDR 0x00104000
319#define PCI_ENET0_MEMADDR 0x80000000
wdenkc6097192002-11-03 00:24:07 +0000320#endif /* __CONFIG_H */