blob: 358fc0208e9b0af82221e35efbdd4df194454c04 [file] [log] [blame]
Joe Hamman9e3ed392007-12-13 06:45:14 -06001/*
2 * Copyright 2007 Wind River Systems <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 * Copyright 2004, 2007 Freescale Semiconductor.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * sbc8548 board configuration file
27 *
28 * Please refer to doc/README.sbc85xx for more info.
29 *
30 */
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/* High Level Configuration Options */
35#define CONFIG_BOOKE 1 /* BOOKE */
36#define CONFIG_E500 1 /* BOOKE e500 family */
37#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
38#define CONFIG_MPC8548 1 /* MPC8548 specific */
39#define CONFIG_SBC8548 1 /* SBC8548 board specific */
40
41#undef CONFIG_PCI /* enable any pci type devices */
42#undef CONFIG_PCI1 /* PCI controller 1 */
43#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
44#undef CONFIG_RIO
45#undef CONFIG_PCI2
46#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */
47
48#define CONFIG_TSEC_ENET /* tsec ethernet support */
49#define CONFIG_ENV_OVERWRITE
50#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
51#define CONFIG_DDR_DLL /* possible DLL fix needed */
52#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
53
54#undef CONFIG_DDR_ECC /* only for ECC DDR module */
55#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
56#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
57#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
58
Kumar Galae2b159d2008-01-16 09:05:27 -060059#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Joe Hamman9e3ed392007-12-13 06:45:14 -060060
61#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
62
63#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */
64
65/*
66 * These can be toggled for performance analysis, otherwise use default.
67 */
68#define CONFIG_L2_CACHE /* toggle L2 cache */
69#define CONFIG_BTB /* toggle branch predition */
70#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
71#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
72
73/*
74 * Only possible on E500 Version 2 or newer cores.
75 */
76#define CONFIG_ENABLE_36BIT_PHYS 1
77
78#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
79
80#undef CFG_DRAM_TEST /* memory test, takes time */
81#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
82#define CFG_MEMTEST_END 0x00400000
83
84/*
85 * Base addresses -- Note these are effective addresses where the
86 * actual resources get mapped (not physical addresses)
87 */
88#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
89#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
Kumar Galaf69766e2008-01-30 14:55:14 -060090#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
Joe Hamman9e3ed392007-12-13 06:45:14 -060091#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
92
93#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
94#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
95#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
96
97/*
98 * DDR Setup
99 */
100#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
101#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
102
103#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
104
105/*
106 * Make sure required options are set
107 */
108#ifndef CONFIG_SPD_EEPROM
109 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */
110#endif
111
112#undef CONFIG_CLOCKS_IN_MHZ
113
114/*
115 * FLASH on the Local Bus
116 * Two banks, one 8MB the other 64MB, using the CFI driver.
117 * Boot from BR0/OR0 bank at 0xff80_0000
118 * Alternate BR6/OR6 bank at 0xfb80_0000
119 *
120 * BR0:
121 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
122 * Port Size = 8 bits = BRx[19:20] = 01
123 * Use GPCM = BRx[24:26] = 000
124 * Valid = BRx[31] = 1
125 *
126 * 0 4 8 12 16 20 24 28
127 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0
128 *
129 * BR6:
130 * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0
131 * Port Size = 32 bits = BRx[19:20] = 11
132 * Use GPCM = BRx[24:26] = 000
133 * Valid = BRx[31] = 1
134 *
135 * 0 4 8 12 16 20 24 28
136 * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6
137 *
138 * OR0:
139 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
140 * XAM = OR0[17:18] = 11
141 * CSNT = OR0[20] = 1
142 * ACS = half cycle delay = OR0[21:22] = 11
143 * SCY = 6 = OR0[24:27] = 0110
144 * TRLX = use relaxed timing = OR0[29] = 1
145 * EAD = use external address latch delay = OR0[31] = 1
146 *
147 * 0 4 8 12 16 20 24 28
148 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0
149 *
150 * OR6:
Jeremy McNicollccf1ad52008-05-02 16:10:04 -0400151 * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600152 * XAM = OR6[17:18] = 11
153 * CSNT = OR6[20] = 1
154 * ACS = half cycle delay = OR6[21:22] = 11
155 * SCY = 6 = OR6[24:27] = 0110
156 * TRLX = use relaxed timing = OR6[29] = 1
157 * EAD = use external address latch delay = OR6[31] = 1
158 *
159 * 0 4 8 12 16 20 24 28
Jeremy McNicollccf1ad52008-05-02 16:10:04 -0400160 * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65 OR6
Joe Hamman9e3ed392007-12-13 06:45:14 -0600161 */
162
163#define CFG_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
164#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */
165
166#define CFG_BR0_PRELIM 0xff800801
167#define CFG_BR6_PRELIM 0xfb801801
168
169#define CFG_OR0_PRELIM 0xff806e65
Jeremy McNicollccf1ad52008-05-02 16:10:04 -0400170#define CFG_OR6_PRELIM 0xf8006e65
Joe Hamman9e3ed392007-12-13 06:45:14 -0600171
Jean-Christophe PLAGNIOL-VILLARD495d1622008-02-17 22:56:16 +0100172#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
Joe Hamman9e3ed392007-12-13 06:45:14 -0600173#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
174#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
175#undef CFG_FLASH_CHECKSUM
176#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
177#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
178
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200179#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600180
181#define CFG_FLASH_CFI_DRIVER
182#define CFG_FLASH_CFI
183#define CFG_FLASH_EMPTY_INFO
184
185/* CS5 = Local bus peripherals controlled by the EPLD */
186
187#define CFG_BR5_PRELIM 0xf8000801
188#define CFG_OR5_PRELIM 0xff006e65
189#define CFG_EPLD_BASE 0xf8000000
190#define CFG_LED_DISP_BASE 0xf8000000
191#define CFG_USER_SWITCHES_BASE 0xf8100000
192#define CFG_BD_REV 0xf8300000
193#define CFG_EEPROM_BASE 0xf8b00000
194
195/*
196 * SDRAM on the Local Bus
197 */
198#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
199#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
200
201/*
202 * Base Register 3 and Option Register 3 configure SDRAM.
203 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
204 *
205 * For BR3, need:
206 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
207 * port-size = 32-bits = BR2[19:20] = 11
208 * no parity checking = BR2[21:22] = 00
209 * SDRAM for MSEL = BR2[24:26] = 011
210 * Valid = BR[31] = 1
211 *
212 * 0 4 8 12 16 20 24 28
213 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
214 *
215 */
216
217#define CFG_BR3_PRELIM 0xf0001861
218
219/*
220 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
221 *
222 * For OR3, need:
223 * 64MB mask for AM, OR3[0:7] = 1111 1100
224 * XAM, OR3[17:18] = 11
225 * 10 columns OR3[19-21] = 011
226 * 12 rows OR3[23-25] = 011
227 * EAD set for extra time OR[31] = 0
228 *
229 * 0 4 8 12 16 20 24 28
230 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
231 */
232
233#define CFG_OR3_PRELIM 0xfc006cc0
234
235#define CFG_LBC_LCRR 0x00000002 /* LB clock ratio reg */
236#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
237#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
238#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
239
240/*
241 * LSDMR masks
242 */
243#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
244#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
245#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
246#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
247#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
248#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
249#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
250#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
251#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
252#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
253
254#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
255#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
256#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
257#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
258#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
259#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
260#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
261#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
262
263/*
264 * Common settings for all Local Bus SDRAM commands.
265 * At run time, either BSMA1516 (for CPU 1.1)
266 * or BSMA1617 (for CPU 1.0) (old)
267 * is OR'ed in too.
268 */
269#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
270 | CFG_LBC_LSDMR_PRETOACT7 \
271 | CFG_LBC_LSDMR_ACTTORW7 \
272 | CFG_LBC_LSDMR_BL8 \
273 | CFG_LBC_LSDMR_WRC4 \
274 | CFG_LBC_LSDMR_CL3 \
275 | CFG_LBC_LSDMR_RFEN \
276 )
277
278#define CONFIG_L1_INIT_RAM
279#define CFG_INIT_RAM_LOCK 1
280#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
281#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
282
283#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
284
285#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
286#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
287#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
288
289#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
290#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
291
292/* Serial Port */
293#define CONFIG_CONS_INDEX 1
294#undef CONFIG_SERIAL_SOFTWARE_FIFO
295#define CFG_NS16550
296#define CFG_NS16550_SERIAL
297#define CFG_NS16550_REG_SIZE 1
298#define CFG_NS16550_CLK 400000000 /* get_bus_freq(0) */
299
300#define CFG_BAUDRATE_TABLE \
301 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
302
303#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
304#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
305
306/* Use the HUSH parser */
307#define CFG_HUSH_PARSER
308#ifdef CFG_HUSH_PARSER
309#define CFG_PROMPT_HUSH_PS2 "> "
310#endif
311
312/* pass open firmware flat tree */
313#define CONFIG_OF_LIBFDT 1
314#define CONFIG_OF_BOARD_SETUP 1
315#define CONFIG_OF_STDOUT_VIA_ALIAS 1
316
317/*
318 * I2C
319 */
320#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
321#define CONFIG_HARD_I2C /* I2C with hardware support*/
322#undef CONFIG_SOFT_I2C /* I2C bit-banged */
323#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
324#define CFG_I2C_EEPROM_ADDR 0x50
325#define CFG_I2C_SLAVE 0x7F
326#define CFG_I2C_OFFSET 0x3000
327
328/*
329 * General PCI
330 * Memory space is mapped 1-1, but I/O space must start from 0.
331 */
332#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
333
334#define CFG_PCI1_MEM_BASE 0x80000000
335#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
336#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
337#define CFG_PCI1_IO_BASE 0x00000000
338#define CFG_PCI1_IO_PHYS 0xe2000000
339#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
340
341#ifdef CONFIG_PCI2
342#define CFG_PCI2_MEM_BASE 0xa0000000
343#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
344#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
345#define CFG_PCI2_IO_BASE 0x00000000
346#define CFG_PCI2_IO_PHYS 0xe2800000
347#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
348#endif
349
350#ifdef CONFIG_PCIE1
351#define CFG_PCIE1_MEM_BASE 0xa0000000
352#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
353#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
354#define CFG_PCIE1_IO_BASE 0x00000000
355#define CFG_PCIE1_IO_PHYS 0xe3000000
356#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
357#endif
358
359#ifdef CONFIG_RIO
360/*
361 * RapidIO MMU
362 */
363#define CFG_RIO_MEM_BASE 0xC0000000
364#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
365#endif
366
367#ifdef CONFIG_LEGACY
368#define BRIDGE_ID 17
369#define VIA_ID 2
370#else
371#define BRIDGE_ID 28
372#define VIA_ID 4
373#endif
374
375#if defined(CONFIG_PCI)
376
377#define CONFIG_NET_MULTI
378#define CONFIG_PCI_PNP /* do pci plug-and-play */
379
380#undef CONFIG_EEPRO100
381#undef CONFIG_TULIP
382
383#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
384
385/* PCI view of System Memory */
386#define CFG_PCI_MEMORY_BUS 0x00000000
387#define CFG_PCI_MEMORY_PHYS 0x00000000
388#define CFG_PCI_MEMORY_SIZE 0x80000000
389
390#endif /* CONFIG_PCI */
391
392
393#if defined(CONFIG_TSEC_ENET)
394
395#ifndef CONFIG_NET_MULTI
396#define CONFIG_NET_MULTI 1
397#endif
398
399#define CONFIG_MII 1 /* MII PHY management */
400#define CONFIG_TSEC1 1
401#define CONFIG_TSEC1_NAME "eTSEC0"
402#define CONFIG_TSEC2 1
403#define CONFIG_TSEC2_NAME "eTSEC1"
404#define CONFIG_TSEC3 1
405#define CONFIG_TSEC3_NAME "eTSEC2"
406#define CONFIG_TSEC4
407#define CONFIG_TSEC4_NAME "eTSEC3"
408#undef CONFIG_MPC85XX_FEC
409
410#define TSEC1_PHY_ADDR 0
411#define TSEC2_PHY_ADDR 1
412#define TSEC3_PHY_ADDR 2
413#define TSEC4_PHY_ADDR 3
414
415#define TSEC1_PHYIDX 0
416#define TSEC2_PHYIDX 0
417#define TSEC3_PHYIDX 0
418#define TSEC4_PHYIDX 0
419#define TSEC1_FLAGS TSEC_GIGABIT
420#define TSEC2_FLAGS TSEC_GIGABIT
421#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
422#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
423
424/* Options are: eTSEC[0-3] */
425#define CONFIG_ETHPRIME "eTSEC0"
426#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
427#endif /* CONFIG_TSEC_ENET */
428
429/*
430 * Environment
431 */
432#define CFG_ENV_IS_IN_FLASH 1
433#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
434#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
435#define CFG_ENV_SIZE 0x2000
436
437#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
438#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
439
440/*
441 * BOOTP options
442 */
443#define CONFIG_BOOTP_BOOTFILESIZE
444#define CONFIG_BOOTP_BOOTPATH
445#define CONFIG_BOOTP_GATEWAY
446#define CONFIG_BOOTP_HOSTNAME
447
448
449/*
450 * Command line configuration.
451 */
452#include <config_cmd_default.h>
453
454#define CONFIG_CMD_PING
455#define CONFIG_CMD_I2C
456#define CONFIG_CMD_MII
457#define CONFIG_CMD_ELF
458
459#if defined(CONFIG_PCI)
460 #define CONFIG_CMD_PCI
461#endif
462
463
464#undef CONFIG_WATCHDOG /* watchdog disabled */
465
466/*
467 * Miscellaneous configurable options
468 */
469#define CFG_LONGHELP /* undef to save memory */
470#define CFG_LOAD_ADDR 0x2000000 /* default load address */
471#define CFG_PROMPT "=> " /* Monitor Command Prompt */
472#if defined(CONFIG_CMD_KGDB)
473#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
474#else
475#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
476#endif
477#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
478#define CFG_MAXARGS 16 /* max number of command args */
479#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
480#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
481
482/*
483 * For booting Linux, the board info and command line data
484 * have to be in the first 8 MB of memory, since this is
485 * the maximum mapped by the Linux kernel during initialization.
486 */
487#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
488
Joe Hamman9e3ed392007-12-13 06:45:14 -0600489/*
490 * Internal Definitions
491 *
492 * Boot Flags
493 */
494#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
495#define BOOTFLAG_WARM 0x02 /* Software reboot */
496
497#if defined(CONFIG_CMD_KGDB)
498#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
499#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
500#endif
501
502/*
503 * Environment Configuration
504 */
505
506/* The mac addresses for all ethernet interface */
507#if defined(CONFIG_TSEC_ENET)
508#define CONFIG_HAS_ETH0
509#define CONFIG_ETHADDR 02:E0:0C:00:00:FD
510#define CONFIG_HAS_ETH1
511#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
512#define CONFIG_HAS_ETH2
513#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD
514#define CONFIG_HAS_ETH3
515#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD
516#endif
517
518#define CONFIG_IPADDR 192.168.0.55
519
520#define CONFIG_HOSTNAME sbc8548
521#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx
522#define CONFIG_BOOTFILE /uImage
523#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
524
525#define CONFIG_SERVERIP 192.168.0.2
526#define CONFIG_GATEWAYIP 192.168.0.1
527#define CONFIG_NETMASK 255.255.255.0
528
529#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
530
531#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
532#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
533
534#define CONFIG_BAUDRATE 115200
535
536#define CONFIG_EXTRA_ENV_SETTINGS \
537 "netdev=eth0\0" \
538 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
539 "tftpflash=tftpboot $loadaddr $uboot; " \
540 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
541 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
542 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
543 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
544 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
545 "consoledev=ttyS0\0" \
546 "ramdiskaddr=2000000\0" \
547 "ramdiskfile=uRamdisk\0" \
548 "fdtaddr=c00000\0" \
549 "fdtfile=sbc8548.dtb\0"
550
551#define CONFIG_NFSBOOTCOMMAND \
552 "setenv bootargs root=/dev/nfs rw " \
553 "nfsroot=$serverip:$rootpath " \
554 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
555 "console=$consoledev,$baudrate $othbootargs;" \
556 "tftp $loadaddr $bootfile;" \
557 "tftp $fdtaddr $fdtfile;" \
558 "bootm $loadaddr - $fdtaddr"
559
560
561#define CONFIG_RAMBOOTCOMMAND \
562 "setenv bootargs root=/dev/ram rw " \
563 "console=$consoledev,$baudrate $othbootargs;" \
564 "tftp $ramdiskaddr $ramdiskfile;" \
565 "tftp $loadaddr $bootfile;" \
566 "tftp $fdtaddr $fdtfile;" \
567 "bootm $loadaddr $ramdiskaddr $fdtaddr"
568
569#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
570
571#endif /* __CONFIG_H */